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please help on verilog and vhdl combination problems

victorhan

Hi Candence,

I met a problem in using verilog and vhdl:

1) I use verilog to make a testbench while the DUT all are made by VHDL

2) I want to initialize the lower level memories in DUT. I have tried to use $nc_mirror, but it seems useless.

So would you like to give me some suggestions on how to initial memories in VHDL designs through  verilog testbench?

Thanks!

Parents

  • I am not sure about the error.I did not inderstand the # in #data[i].

    data[i] also needs to be in  " ".

    nc_force command has to be like this.

    If your memarray is of size 5,each single bit

    $nc_force("tb_top.vhdl_top:ocmem:memarry" , "10010"); //if it is a single bit. 

    Regards,

    Shalem

Reply

  • I am not sure about the error.I did not inderstand the # in #data[i].

    data[i] also needs to be in  " ".

    nc_force command has to be like this.

    If your memarray is of size 5,each single bit

    $nc_force("tb_top.vhdl_top:ocmem:memarry" , "10010"); //if it is a single bit. 

    Regards,

    Shalem

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