I'm trying to use verilog generic on my vhdl instance via the defparam option of ncelab and I get the following message:
"Attempted propagation of defparam results to a non-Verilog instance"
The generic in my dut instance are not set and use the default value. Is that not supported?
module tb_top; parameter G_DATA_WIDTH = 8;
wire [G_DATA_WIDTH-1:0] data_in;
wire [G_DATA_WIDTH-1:0] data_out;
/* DUT */ top #(.G_DATA_WIDTH (G_DATA_WIDTH)) my_dut ( .clk (clk), .data_in (data_in), .data_out (data_out), );endmodule
Thank you for the help
NC as a tool does not allow you to propagate the new value across the language boundary. The default initial value of the parameter is taken as its value. The defparam statement tries to re-propagate the value of G_DATA_WIDTH in the VHDL instance and this warning suggests that the tool is not able to do so and retains the value of G_DATA_WIDTH to be 8 only.A VHDL generic is an elaboration time constant and we do not have a way to re-evaluate it based on a new defparam statement. To work around this, you can use the "-gpg" flag or a combination of “-defparam/-generic” options . % irun -mess ...... -generic "tb_top.my_dut.G_DATA_WIDTH => 16"Or% irun -mess ...... -gpg "tb_top.my_dut:G_DATA_WIDTH => 16"
Thank you Muffi, it helps!
But, that sounds like a missing feature for me, is there plans to support that later? Synopsys VCS and modelsim support that for instance. If one wants to migrate from one of these tools to cadence, this would give quite a lot of work to get the elaboration up and running.
Defparam is going to be a deprecated feature from the new Verilog LRM perspective. See section C.4.1 - Defparam statements.From a re-usability of code perspective, defparams are not the ideal solution and should be avoided.
So using the "-gpg" or a combination of "-defparam/-generic" options should be a clean solution to avoid this warning