I'm trying to use verilog generic on my vhdl instance via the defparam option of ncelab and I get the following message:
"Attempted propagation of defparam results to a non-Verilog instance"
The generic in my dut instance are not set and use the default value. Is that not supported?
module tb_top; parameter G_DATA_WIDTH = 8;
wire [G_DATA_WIDTH-1:0] data_in;
wire [G_DATA_WIDTH-1:0] data_out;
/* DUT */ top #(.G_DATA_WIDTH (G_DATA_WIDTH)) my_dut ( .clk (clk), .data_in (data_in), .data_out (data_out), );endmodule
Thank you for the help
Thank you Muffi, it helps!
But, that sounds like a missing feature for me, is there plans to support that later? Synopsys VCS and modelsim support that for instance. If one wants to migrate from one of these tools to cadence, this would give quite a lot of work to get the elaboration up and running.