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How to disable automatically-generated cross bins?

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 Consider the following example code:(it's an example in SystemVerilog P1800-2009, Page 500)

int i,j;
covergroup ct;
coverpoint i { bins i[] = { [0:1] }; }
coverpoint j { bins j[] = { [0:1] }; }
x1: cross i,j;
x2: cross i,j {
bins i_zero = binsof(i) intersect { 0 };
}
endgroup

Cross x2 has the following bins:
i_zero // user-specified bin for
(i[1],j[0]) // an automatically-generated bin that is retained
(i[1],j[1]) // an automatically-generated bin that is retained

My question is: if I only want the first bin, i.e. i_zero, what should I do? I don't want automatically-generated cross bins, I just want user-defined bins, is there some method to disable "automatically-generated cross bins"?

Thanks a lot!

  • We have provided support for a new option "option.cross_auto_bin_max" for crosses in 12.10 -s13 release.

    The cross_auto_bin_max option is defined at the covergroup level. So, the value of cross_auto_bin_max at covergoup level will propagate to cross level and total number of cross autobins will be 0. This option takes '0' as the only possible value else an error will be reported by the tool.

    If option.cross_auto_bin_max=0 is specified in a cross definition then none of the cross autobins will be saved in the database and will not be reported as well.

    Hope this helps.

  •  Hi, muffi:

    Thanks for your reply. This option is just what I wanted! It works well.

    But I have another question: you said that this option is defined at the covergroup level, but I can use this option in cross level. My tool does not report error, and the coverage report is just what I expected. My EDA tool is irun(64): 12.20-s014.

    Actually, if this option can only be defined at covergroup level, it comes a big problem!  In my covergroup, there are other cross coverages, I don't want those cross coverage be effected by this option(cross_auto_bin_max = 0).

     

  • This option works at cross level too.

  • Hi, Muffi:

    Another question, hope that I do not disturb you. :)

    I can find this option(cross_auto_bin_max) in SystemVerilog LRM 3.1a, but I can't find it in P1800-2005, P1800-2009, P1800-2012. Wh? Does this a option related tools but not language? I think this option should be a feature of Systemverilog, but not EDA tools, am I right?

    Thanks!

  • You are right. This option was part of Accellera 3.1 standard. But it was removed starting from P1800 2005 version of LRM. It is now a tool specific feature.

     http://www.eda.org/svdb/view.php?id=641

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