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  3. How to disable automatically-generated cross bins?

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How to disable automatically-generated cross bins?

archive
archive over 11 years ago

 Consider the following example code:(it's an example in SystemVerilog P1800-2009, Page 500)

int i,j;
covergroup ct;
coverpoint i { bins i[] = { [0:1] }; }
coverpoint j { bins j[] = { [0:1] }; }
x1: cross i,j;
x2: cross i,j {
bins i_zero = binsof(i) intersect { 0 };
}
endgroup

Cross x2 has the following bins:
i_zero // user-specified bin for
(i[1],j[0]) // an automatically-generated bin that is retained
(i[1],j[1]) // an automatically-generated bin that is retained

My question is: if I only want the first bin, i.e. i_zero, what should I do? I don't want automatically-generated cross bins, I just want user-defined bins, is there some method to disable "automatically-generated cross bins"?

Thanks a lot!

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  • muffi
    muffi over 11 years ago

    You are right. This option was part of Accellera 3.1 standard. But it was removed starting from P1800 2005 version of LRM. It is now a tool specific feature.

     http://www.eda.org/svdb/view.php?id=641

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  • muffi
    muffi over 11 years ago

    You are right. This option was part of Accellera 3.1 standard. But it was removed starting from P1800 2005 version of LRM. It is now a tool specific feature.

     http://www.eda.org/svdb/view.php?id=641

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