I have a question while using IFV, there is a simulation model in my design, after running the verification flow for several cycles, I did not find PRINET was set to 1b'1, this seems to be the issue related with initial statement, I do not know how to slove, could you help me? Thank you!
module PRI(PRI); input PRI;parameter RST_PULSE = 1;reg PRINET;initialbegin PRINET = 1'b0; #RST_PULSE PRINET = 1'b1;endendmodule
=========================TCL script file=========================
clock -add ck -initial 1 -width 1 -period 2
IFV workd with a model built from the synthesized RTL design. Initial blocks are ignored by IFV because they are not part of the synthesized circuit. The workaround is to add the statements to your initialization sequence and constraints.
force PRINET 0force resetn 0run 2const -add -pin resetn 1 -resetconst -add -pin PRINET 1'b1
Thank you TAM1, you save me again!
BTW, if there is a large design with an initial blocks in some module, it would cause problems if the IFV engineer does not know this, right? If so, how to avoid this risk?
No one should design hardware that depends on an initial block to work correctly. Initial blocks in design RTL are often forbidden by design methodologies for just this reason.
Yes, I totally agree with you, based on this, if I want to verify a design with some simulation modles(e.g., DDR momory, PCI slave device), it's impractical to apply the IFV to the whole testbench? since these simulation modles may have some unsynthesizable statements. Do you mean that I still need to use the "irun"?
One applies the formal tool to the DUT itself. There should be no testbench involved. IFV applies all possible stimulus to the design (subject to the constraints), so no testbench should be involved.
If IFV finds that parts of the design itself are not synthesizable, it will complain loudly and "black-box" them. That means it will drop them from the analysis and make no assumptions about their outputs.
If you want to analyze a block that communicates to a memory or across a particular protocol, then things get more complex. You don't necessarily need a fully synthesizable model of the connected block. But you do need some kind of IP that will model that memory or protocol for the formal tool. Some vendors can sell you a set of assertions that define a properly behaving AHB interface, for example. If you apply those assertions to the port on the DUT, then you don't need an actual simulation model. Others may provide a light-weight synthesizable model of the slave that doesn't do anything more than respond correctly to the master. The same applies to a memory.