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merging three worklibs into one

usha sudhagar

we have a issue in merging 3 worklib( worklib_1,worklib_2,worklib_3 which has been created during compilation) during elaboration phase.

Command used for creating those worklib is:(top file - system.sv)

ncverilog -compile +ncaccess+c +notimingchecks -timescale 1ns/10ps +licq_ncv  -l verilog1.log -work worklib_1 -input ius.tcl -f verilog_1.f

ncverilog -compile +ncaccess+c +notimingchecks -timescale 1ns/10ps +licq_ncv -l verilog1.log -work worklib_2 -input ius.tcl -f verilog_2.f

ncverilog -compile +ncaccess+c +notimingchecks -timescale 1ns/10ps +licq_ncv -l verilog1.log -work worklib_3 -input ius.tcl -f verilog_3.f 

Command used for elaboration is:

ncelab worklib_1.system -cdslib ../simh/INCA_libs/irun.lnx8664.10.20.nc/cds.lib -hdlvar ../simh/INCA_libs/irun.lnx8664.10.20.nc/hdl.var -snapshot system:snapshot

we are getting the below error

ncelab: *E,NOUNIT: Unable to find a unit named 'worklib.system' in the libraries.

can anyone help us in solving the above error by providing the proper solution

Parents

  • Without seeing what's in your *.f files it's not possible to give a precise answer. What I would say however is: try switching to the "irun" flow instead of calling ncverilog and ncelab separately. Secondly, you are using a very old release whihc is no longer supported. You may come across bugs that have been fixed in more recent releases.

    I would suggest the following irun use model based on your example:

     irun -c -access +c -notimingchecks -timescale 1ns/10ps -makelib worklib_1 -f verilog_1.f -endlib -makelib worklib_2 -f verilog_2.f -endlib -makelib worklib_3 -f verilog_3.f -endlib -top worklib_1.system

    This handles making the library directories for you. You would then run the compiled design with "irun -R [-gui]".

    FYI, the +licq_ncv and -input options will have no effect on your compilation command - these only apply to simulation.

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  • Without seeing what's in your *.f files it's not possible to give a precise answer. What I would say however is: try switching to the "irun" flow instead of calling ncverilog and ncelab separately. Secondly, you are using a very old release whihc is no longer supported. You may come across bugs that have been fixed in more recent releases.

    I would suggest the following irun use model based on your example:

     irun -c -access +c -notimingchecks -timescale 1ns/10ps -makelib worklib_1 -f verilog_1.f -endlib -makelib worklib_2 -f verilog_2.f -endlib -makelib worklib_3 -f verilog_3.f -endlib -top worklib_1.system

    This handles making the library directories for you. You would then run the compiled design with "irun -R [-gui]".

    FYI, the +licq_ncv and -input options will have no effect on your compilation command - these only apply to simulation.

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