merging three worklibs into one

Without seeing what's in your *.f files it's not possible to give a precise answer. What I would say however is: try switching to the "irun" flow instead of calling ncverilog and ncelab separately. Secondly, you are using a very old release whihc is no longer supported. You may come across bugs that have been fixed in more recent releases.

I would suggest the following irun use model based on your example:

 irun -c -access +c -notimingchecks -timescale 1ns/10ps -makelib worklib_1 -f verilog_1.f -endlib -makelib worklib_2 -f verilog_2.f -endlib -makelib worklib_3 -f verilog_3.f -endlib -top worklib_1.system

This handles making the library directories for you. You would then run the compiled design with "irun -R [-gui]".

FYI, the +licq_ncv and -input options will have no effect on your compilation command - these only apply to simulation.

thanks for ur reply... 

Please find the example below.

file list verilog_1.f contains only one file named system.sv,  file list verilog_2.f contain files named multiple.v and divider.v , file list verilog_3.f contains only one file named adder.vhd

system.sv  code:

module system();

int a,b,out;

multiple m1(out,a,b);

....

endmodule

multiple.v code

module multiple(output cc,input aa,bb);

reg[31:0] sum;

reg carry;

adder u_adder(aa,bb,sum,carry);

....

endmodule

adder.vhd is a vhd file .

we tried with the command:

irun  -v200x -c -access +c -notimingchecks -timescale 1ns/10ps -makelib worklib_3 -f verilog_3.f -endlib -work worklib_2 -f verilog_2.f -makelib worklib_1 system.sv -endlib

And now,we are getting following ERROR:

 ncelab: *E,MULVHD: Possible bindings for instance of entity 'adder' in 'worklib_2.multiple:v' are:
         WORKLIB_3.ADDER:RTL
          .
 adder u_adder(
                           |
ncelab: *E,CUVMUR (multiple.v,3483|22): instance 'm1.u_adder' of design unit 'adder' is unresolved in 'worklib_2.multiple:v'.

It seems to be that the  libraries worklib_3 and worklib_2 are not binded.Please provide the appropriate suggestion/solution for binding the libraries. 

 Right...

I would recommend that you do not use multiple work libraries then. Verilog isn't really set up for this the way VHDL is, so in general it's best to compile all your Verilog / SV code into a single work library.

Try this command:

irun -c -access +c -notimingchecks -timescale 1ns/10ps -f verilog_1.f -f verilog_2.f -f verilog_3.f system.sv

By the way,"-access -c" only enables connectivity tracing acess into the design, you might want "-access +rc" so that you can probe signals into the waveform database as well.