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merging three worklibs into one

usha sudhagar

we have a issue in merging 3 worklib( worklib_1,worklib_2,worklib_3 which has been created during compilation) during elaboration phase.

Command used for creating those worklib is:(top file - system.sv)

ncverilog -compile +ncaccess+c +notimingchecks -timescale 1ns/10ps +licq_ncv  -l verilog1.log -work worklib_1 -input ius.tcl -f verilog_1.f

ncverilog -compile +ncaccess+c +notimingchecks -timescale 1ns/10ps +licq_ncv -l verilog1.log -work worklib_2 -input ius.tcl -f verilog_2.f

ncverilog -compile +ncaccess+c +notimingchecks -timescale 1ns/10ps +licq_ncv -l verilog1.log -work worklib_3 -input ius.tcl -f verilog_3.f 

Command used for elaboration is:

ncelab worklib_1.system -cdslib ../simh/INCA_libs/irun.lnx8664.10.20.nc/cds.lib -hdlvar ../simh/INCA_libs/irun.lnx8664.10.20.nc/hdl.var -snapshot system:snapshot

we are getting the below error

ncelab: *E,NOUNIT: Unable to find a unit named 'worklib.system' in the libraries.

can anyone help us in solving the above error by providing the proper solution

Parents

  •  Right...

    I would recommend that you do not use multiple work libraries then. Verilog isn't really set up for this the way VHDL is, so in general it's best to compile all your Verilog / SV code into a single work library.

    Try this command:

    irun -c -access +c -notimingchecks -timescale 1ns/10ps -f verilog_1.f -f verilog_2.f -f verilog_3.f system.sv

     

    By the way,"-access -c" only enables connectivity tracing acess into the design, you might want "-access +rc" so that you can probe signals into the waveform database as well.

Reply

  •  Right...

    I would recommend that you do not use multiple work libraries then. Verilog isn't really set up for this the way VHDL is, so in general it's best to compile all your Verilog / SV code into a single work library.

    Try this command:

    irun -c -access +c -notimingchecks -timescale 1ns/10ps -f verilog_1.f -f verilog_2.f -f verilog_3.f system.sv

     

    By the way,"-access -c" only enables connectivity tracing acess into the design, you might want "-access +rc" so that you can probe signals into the waveform database as well.

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