merging three worklibs into one

thanks for ur reply... 

Please find the example below.

file list verilog_1.f contains only one file named system.sv,  file list verilog_2.f contain files named multiple.v and divider.v , file list verilog_3.f contains only one file named adder.vhd

system.sv  code:

module system();

int a,b,out;

multiple m1(out,a,b);

....

endmodule

multiple.v code

module multiple(output cc,input aa,bb);

reg[31:0] sum;

reg carry;

adder u_adder(aa,bb,sum,carry);

....

endmodule

adder.vhd is a vhd file .

we tried with the command:

irun  -v200x -c -access +c -notimingchecks -timescale 1ns/10ps -makelib worklib_3 -f verilog_3.f -endlib -work worklib_2 -f verilog_2.f -makelib worklib_1 system.sv -endlib

And now,we are getting following ERROR:

 ncelab: *E,MULVHD: Possible bindings for instance of entity 'adder' in 'worklib_2.multiple:v' are:
         WORKLIB_3.ADDER:RTL
          .
 adder u_adder(
                           |
ncelab: *E,CUVMUR (multiple.v,3483|22): instance 'm1.u_adder' of design unit 'adder' is unresolved in 'worklib_2.multiple:v'.

It seems to be that the  libraries worklib_3 and worklib_2 are not binded.Please provide the appropriate suggestion/solution for binding the libraries. 

thanks for ur reply... 

Please find the example below.

file list verilog_1.f contains only one file named system.sv,  file list verilog_2.f contain files named multiple.v and divider.v , file list verilog_3.f contains only one file named adder.vhd

system.sv  code:

module system();

int a,b,out;

multiple m1(out,a,b);

....

endmodule

multiple.v code

module multiple(output cc,input aa,bb);

reg[31:0] sum;

reg carry;

adder u_adder(aa,bb,sum,carry);

....

endmodule

adder.vhd is a vhd file .

we tried with the command:

irun  -v200x -c -access +c -notimingchecks -timescale 1ns/10ps -makelib worklib_3 -f verilog_3.f -endlib -work worklib_2 -f verilog_2.f -makelib worklib_1 system.sv -endlib

And now,we are getting following ERROR:

 ncelab: *E,MULVHD: Possible bindings for instance of entity 'adder' in 'worklib_2.multiple:v' are:
         WORKLIB_3.ADDER:RTL
          .
 adder u_adder(
                           |
ncelab: *E,CUVMUR (multiple.v,3483|22): instance 'm1.u_adder' of design unit 'adder' is unresolved in 'worklib_2.multiple:v'.

It seems to be that the  libraries worklib_3 and worklib_2 are not binded.Please provide the appropriate suggestion/solution for binding the libraries.