Problem when running simulation with Verilog-AMS and SystemVerilog together with irun

solomonchoi said:

 Hi,

 I am now working on a AMS verification using irun. I have an analog module (Verilog-AMS model, .vams) and a logic module (SystemVerilog RTL netlist, .sv) and want to integrate them together for system verification, especially on the control of the analog module by the logic one. The testbench I am using is in .vams format. When I compiled it with irun, it gave the following error message and I don't know how to fix it. May I know if you have an idea on this issue? Thanks a lot in advance.

 ncvlog: *E,WOUPSR (/rtl/sv/dtcm_dsc_enc_ich.sv,293|27): A reference to an entire array is not permitted in this context [SystemVerilog].
(`include file: /rtl/sv/dtcm_dsc_enc_ich.sv line 372, file: all.sv line 121)
        history[i] = history_m[i];

Best Regards,

Solomon

The extended help for that error gives slightly more information to help you. Otherwise without seeing your code it's not rteally possible to answer that question.

 % nchelp ncelab WOUPSR
nchelp: 13.20-s010: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
ncelab/WOUPSR =
        This particular context does not permit a reference to a whole
        unpacked array, unpacked struct or union.
        We currently do not support multi dimensional fixed wire arrays on port connections.

Hi Stephen,

This is part of our code on the instantiation and the module definition relating to the error. Actually, I found that unpacked wire array ports are said to be prohibited to be connected to VHDL or Verilog AMS in Cadence's SystemVerilog Reference. Does it mean that this is not supported? Thanks for your help!

wire [26:0] history_m [31:0];

dsc_enc_ich_mux  dsc_enc_ich_mux (
    .clk          (clk),
    .rst_b        (rst_b),
    .sync_rst     (sync_rst),

    .idx0         (ich_idx_d1[0]),
    .idx1         (ich_idx_d1[1]),
    .idx2         (ich_idx_d1[2]),
   
    .histbuf      (histbuf),

    .history      (history_m)
); 

module dsc_enc_ich_mux #(
) (
    input        clk,
    input        rst_b,
    input        sync_rst,

    input  [4:0] idx0,
    input  [4:0] idx1,
    input  [4:0] idx2,
   
    input [26:0] histbuf [31:0],

    output reg [26:0] history [31:0]
);
 

There are no industry-standard specifications for the way the different languages connect together, e.g. VHDL to Verilog or AMS, so if the docs say it's prohibited it would generally mean it's something that's limited by the tool implementation instead of by a standard.

In your specific case I have a suspicion that the problem comes from your declaration of  "output reg [26:0] history [31:0]". If possible, try changing this to a wire declaration like "output wire [26:0] history [31:0]", then use a continuous assignment from a new internal reg signal onto the wire port. I can't promise that will fix your issue, but it does look like a limitation that another customer showed me this week, and which I'm still investigating.

Alternatively change the unpacked declaration to a packed one: "output reg [26:0][31:0] history".

If you do try this, please share the result here for others to benefit.