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Problem when running simulation with Verilog-AMS and SystemVerilog together with irun

solomonchoi

 Hi,

 I am now working on a AMS verification using irun. I have an analog module (Verilog-AMS model, .vams) and a logic module (SystemVerilog RTL netlist, .sv) and want to integrate them together for system verification, especially on the control of the analog module by the logic one. The testbench I am using is in .vams format. When I compiled it with irun, it gave the following error message and I don't know how to fix it. May I know if you have an idea on this issue? Thanks a lot in advance.

 ncvlog: *E,WOUPSR (/rtl/sv/dtcm_dsc_enc_ich.sv,293|27): A reference to an entire array is not permitted in this context [SystemVerilog].
(`include file: /rtl/sv/dtcm_dsc_enc_ich.sv line 372, file: all.sv line 121)
        history[i] = history_m[i];

Best Regards,

Solomon

Parents

  • Hi Stephen,

    This is part of our code on the instantiation and the module definition relating to the error. Actually, I found that unpacked wire array ports are said to be prohibited to be connected to VHDL or Verilog AMS in Cadence's SystemVerilog Reference. Does it mean that this is not supported? Thanks for your help!

     

    wire [26:0] history_m [31:0];

    dsc_enc_ich_mux  dsc_enc_ich_mux (
        .clk          (clk),
        .rst_b        (rst_b),
        .sync_rst     (sync_rst),

        .idx0         (ich_idx_d1[0]),
        .idx1         (ich_idx_d1[1]),
        .idx2         (ich_idx_d1[2]),
       
        .histbuf      (histbuf),

        .history      (history_m)
    ); 

    module dsc_enc_ich_mux #(
    ) (
        input        clk,
        input        rst_b,
        input        sync_rst,

        input  [4:0] idx0,
        input  [4:0] idx1,
        input  [4:0] idx2,
       
        input [26:0] histbuf [31:0],

        output reg [26:0] history [31:0]
    );
     

Reply

  • Hi Stephen,

    This is part of our code on the instantiation and the module definition relating to the error. Actually, I found that unpacked wire array ports are said to be prohibited to be connected to VHDL or Verilog AMS in Cadence's SystemVerilog Reference. Does it mean that this is not supported? Thanks for your help!

     

    wire [26:0] history_m [31:0];

    dsc_enc_ich_mux  dsc_enc_ich_mux (
        .clk          (clk),
        .rst_b        (rst_b),
        .sync_rst     (sync_rst),

        .idx0         (ich_idx_d1[0]),
        .idx1         (ich_idx_d1[1]),
        .idx2         (ich_idx_d1[2]),
       
        .histbuf      (histbuf),

        .history      (history_m)
    ); 

    module dsc_enc_ich_mux #(
    ) (
        input        clk,
        input        rst_b,
        input        sync_rst,

        input  [4:0] idx0,
        input  [4:0] idx1,
        input  [4:0] idx2,
       
        input [26:0] histbuf [31:0],

        output reg [26:0] history [31:0]
    );
     

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