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Binding systemverilog modules (module ports' directions)

mkamal

Hello,

I'm using some binding modules in sytemverilog VIP. They are binded to VHDL modules.

The systemverilog modules' ports are all defined as logic without  specifying direction (input, output or inout).

Compilation passes without any errors. Elaboration fails. It requires direction to be specified for some ports in sys-verilog bind modules definitions as te direction for the VHDL modules.

This isn't the case with modelsim which doesn'r produce elaboration errors.

Also Why this is required for some ports and not all the ports ?

The error code is: ncvhdl_p: *E,CFMPMC

And an example on the eror msg is: "(./INCA_libs/irun.lnx8664.11.10.nc/.cdssvbind/cds_tmp_svbind0000422d_a8c0620a_0x2a003d41.sva,2|762): Port mode mismatch: Verilog(fsm_sink_bind.send_ack) is mode 'input'; VHDL(FSM.SEND_ACK) is mode 'out'."

Note that it says  fsm_sink_bind.send_ack direction is "input", although I declare it as logic without specifying direction !

 

Parents
  • Input is implied for ports where you don't give the direction. In your case, it seems like you're trying to connect a VHDL output of the block to a bind module input. In VHDL, connecting an output to an internal signal is illegal. Incisive just enforces that rule regardless if this internal signal is a VHDL signal or an SV signal in a bound module, whereas Questa does not.
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  • Input is implied for ports where you don't give the direction. In your case, it seems like you're trying to connect a VHDL output of the block to a bind module input. In VHDL, connecting an output to an internal signal is illegal. Incisive just enforces that rule regardless if this internal signal is a VHDL signal or an SV signal in a bound module, whereas Questa does not.
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