I'm using some binding modules in sytemverilog VIP. They are binded to VHDL modules.
The systemverilog modules' ports are all defined as logic without specifying direction (input, output or inout).
Compilation passes without any errors. Elaboration fails. It requires direction to be specified for some ports in sys-verilog bind modules definitions as te direction for the VHDL modules.
This isn't the case with modelsim which doesn'r produce elaboration errors.
Also Why this is required for some ports and not all the ports ?
The error code is: ncvhdl_p: *E,CFMPMC
And an example on the eror msg is: "(./INCA_libs/irun.lnx8664.11.10.nc/.cdssvbind/cds_tmp_svbind0000422d_a8c0620a_0x2a003d41.sva,2|762): Port mode mismatch: Verilog(fsm_sink_bind.send_ack) is mode 'input'; VHDL(FSM.SEND_ACK) is mode 'out'."
Note that it says fsm_sink_bind.send_ack direction is "input", although I declare it as logic without specifying direction !
Hi Steve, I am having this same problem but the two options you mentioned do not work. Is there a more up-to-date option I can use to allow binding of a Verilog module, with input ports only, to a VHDL module with a mixture of input and output ports?
Hi Leo. When you say these don't work, do you mean they cause errors, or are they accepted but don't have the desired effect? Are you able to share an example code or the error you're getting?
Hi Steve. They don't give the desired effect. The error message remains the same.