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Binding systemverilog modules (module ports' directions)

mkamal

Hello,

I'm using some binding modules in sytemverilog VIP. They are binded to VHDL modules.

The systemverilog modules' ports are all defined as logic without  specifying direction (input, output or inout).

Compilation passes without any errors. Elaboration fails. It requires direction to be specified for some ports in sys-verilog bind modules definitions as te direction for the VHDL modules.

This isn't the case with modelsim which doesn'r produce elaboration errors.

Also Why this is required for some ports and not all the ports ?

The error code is: ncvhdl_p: *E,CFMPMC

And an example on the eror msg is: "(./INCA_libs/irun.lnx8664.11.10.nc/.cdssvbind/cds_tmp_svbind0000422d_a8c0620a_0x2a003d41.sva,2|762): Port mode mismatch: Verilog(fsm_sink_bind.send_ack) is mode 'input'; VHDL(FSM.SEND_ACK) is mode 'out'."

Note that it says  fsm_sink_bind.send_ack direction is "input", although I declare it as logic without specifying direction !

 

Parents
  • If you compile your code witht he -v200x option it should work, as this allows VHDL output ports to be read, per the more recent VHDL standard. If you need to compile hte VHDL in 87 or 93 mode, then don't use -v200x, just use "-controlrelax OUTPREAD" which turns off the check for reading output ports.
  • in reply to StephenH

    Hi Steve,  I am having this same problem but the two options you mentioned do not work.  Is there a more up-to-date option I can use to allow binding of a Verilog module, with input ports only, to a VHDL module with a mixture of input and output ports?

  • in reply to LeoMatturi

    Hi Leo. When you say these don't work, do you mean they cause errors, or are they accepted but don't have the desired effect? Are you able to share an example code or the error you're getting?

  • in reply to StephenH

    Hi Steve.  They don't give the desired effect.  The error message remains the same.

  • in reply to LeoMatturi

    I think I have a workaround now.  The signals appear to exist lower down in the hierarchy where there are Verilog sigs.  I will bind to the lower module.  

    xmvhdl_p: *E,CFMPMC (./xcelium.d/run.lnx8664<deleted by Leo>/.cdssvbind/cds_tmp_svbind00005f9d_1dac2dcf_0x6317a2bc.sva,3|124): Port mode mismatch: Verilog(<deleted by Leo>_rd_n_wr__if.rd_n_o) is mode 'inout'; VHDL(IP_TC18.<deletet by Leo>RD_N_O) is mode 'out'.

  • in reply to LeoMatturi

    Hmmm... Are you using a very old simulator version? "cdssvbind" is an artefact of the old binding mechanism from about 5 years ago; it got replaced with a new native bind architecture that works much better. You could try the -nncbind switch with Incisive, or -nxmbind with older Xceliums. This switch became a default a while ago but should be supported as a no-op anyway.

    Anyway, the old bind architecture may well have problems with cross-language binding, we would need a testcase to know if that's your exact problem though...

  • in reply to StephenH

    Yes, I will note the details of the issue down and raise a case later on.  I will also take note of these other options.

    The binding has been moved to a lower level Verilog file which does not exhibit this problem.  I can now make progress.  When I have completed the SVA task then I will see if I can raise the support ticket and attach a testcase.  Thanks for your help.  

Reply
  • in reply to StephenH

    Yes, I will note the details of the issue down and raise a case later on.  I will also take note of these other options.

    The binding has been moved to a lower level Verilog file which does not exhibit this problem.  I can now make progress.  When I have completed the SVA task then I will see if I can raise the support ticket and attach a testcase.  Thanks for your help.  

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