Connecting VHDL port to system verilog interface definition in UVM

I have a package definition in VHDL which contains the user defined array type which is the output of my DUT.The definition is as below:

TYPE loop_reg_ty IS RECORD
      loop_index_value    : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
      loop_counter : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
      loop_end_flag : std_logic;
END RECORD;

TYPE loop_array_ty is array (MAX_NO_OF_LOOPS-1 downto 0) of std_logic_vector(REG_BITWIDTH-1 downto 0);

I read in other posts that cadence doesn't support importing the package into system verilog environment and hence i am trying to define the similar structure in system verilog environment as below : 

typedef struct packed {
                            bit [REG_BITWIDTH-1:0] loop_index_value;
                            bit [REG_BITWIDTH-1:0] loop_counter;
                            bit loop_end_flag;
                          } raccu_loop_reg_ty;

typedef loop_reg_ty [MAX_NO_OF_RACCU_LOOPS-1:0] loop_array_ty;

But during elaboration i am getting the error as below :


ncelab: *E,CFMPTC  : VHDL port type is not compatible with Verilog.

Please let me know the possible work around solution for this.