Controlling Seed to multi langauge verification environment

As far as I'm aware, srand() would not be modified / re-implemented by the simulator so you'll be getting the default seed (1) unless you explicitly seed srand() itself, as per "man srand". Note the caveats in the man page regarding the lack of thread safety and hence stability of the sequence generated.

You should really consider generating all your random numbers in SV, certainly if you want any kind of constraint on the sequence you really do not want to be doing this in C++!

If you have random generation in SV and in C++, it will be hard for you to ensure the random sequence is stable and repeatable for debugging, whereas in SV and UVM this would be taken care of for you.

Hi stephen

        Thanks for your reply. I am not very familiary with C++. From you mail my understanding is that if we dont specify a number while calling srand function then default seed value is 1 and it will produce same results everytime we call the function. i,e, srand(). If we call srand function with some random number, then every time the random number changes the result from srand function also change. i.e. srand(<random_value>) right? . And we can not control randomization in C++ model from simulator (Incisive) even if we are executing C++ model through DPI from simulator. We have do all randomization in UVM/E  when we are using C++ model in verification env else it will be hard to reproduce same senarios. Please let me know if my understanding is correct?

 - regards

To be perfectly honest I'm not really familiar with doing randomisation in C++ either, there's no need when e and SV have such powerful randomisation capabilities. From looking at the man page for rand() and srand(), it looks like you get the default seed of 1 every time you start the program, unless you re-seed it with srand. You only use srand() once to set the seed, thereafter you call rand() to get the next random number in the sequence.

Now, returning to your question about where to do the randomisation, I would recommend doing it all in your chosen verification language (SV or e) because as I said, you have tool-provided random stability, you get constraint-based randomisation and you get a debugger for the randomisation. In contrast in C/C++ you get no guarantee of random stability (depends on how you interact with the model), nothing but basic random integers, no constraint syntax and no debugger.

I would also question whether you "model" is truly a model (in the which case why is it doing ANY randomisation)? We normally refer to a model as something that mimics the behaviour of the DUT so that we can predict the RTL outputs. If you really meant a BFM or other stimulus generator then I can understand why you want randomisation, but again I'd suggest that you code as much as possible in e or SV so that all of your stimulus can be controlled in the normal UVM fashion, top-down and coordinated by sequences. If you have even one component in C++ doing its own thing and not directly controlled by UVM sequences, it'll be really hard to write tests and to debug.

Hi Stephen

       Thanks for your reply again and also for the detailed explanation :)  The DUT model in C++ i received from another team member so i am not sure why he used srand function in it. Will confirm with him about it. As you suggested will try to do all randomization in SV. Thanks again for you time and response.

 - regards

Hi Stepehen

           We are verifying receiver part of an IP. The C++ model we got have both TX and RX part of the system . Tx part use the srand function to generate the random data. We are thinking of passing the random from the system verilog environment to the C model for srand function. I am thinking of using the SVSEED generated by the incisive tool to pass to the C++ model. Is it possible to get the SVSEED from SV environment.

 - regards