Forcing Verilog signal simple_port with pli_access == TRUE in Specman

Hi Michael,

you can use a simple indexed_port (without any index) to access a signal/wire. For those the combination of pli_access() and force/release is supported. This is documented in the Specman Integrators guide under:
6.4.6 Forcing and Releasing SystemVerilog Objects Accessed with e Simple Indexed Ports

-hannes

Hi Hannes,

Thanks for the response. I am aware of the unsupported combination, but I still need to force a signal that has pli_access() set to TRUE. Maybe I am misunderstanding what pli_access() does... Are there any workarounds or constructs that specman provides for anyone who has this specific use case of needing to force a signal while pli_access() is TRUE?

Thanks,

Michael

Hi Michael,

maybe there was a misunderstanding, but what I wrote in the last mail is a viable workaround. The combination of indexed_port with the pli_access attribute and the use of force/release is supported and this enables you to force a signal.

Maybe some example code would help:

<' // t1.e
method_type w_pli();

extend sys {

  wp: simple_port (w_pli) of int is instance;
  keep wp.pli_access()==TRUE;
  keep wp.hdl_path() == "~/top/wp";

  clk_rise: in event_port is instance;
  keep clk_rise.hdl_path() == "~/top/clk";
  keep clk_rise.edge() == rise;

  run() is also {
    start tcm();
  };

  tcm()@clk_rise$ is {
    while TRUE {
      if (sys.time > 500) {
        stop_run();
      };
      if (sys.time == 250 ) {
        force wp.index()$=55;
      };
      if (sys.time == 450 ) {
        release wp.index();
      };
      wait [2];
    };
  };
};

'>
---- ex.v----

module top;
  wire [31:0] wp;
  reg clk;

  initial clk = 0;
  always #50 clk = ~clk;

endmodule

Regards,
-hannes

Oh I see. Yeah, I did misread your last post. This is exactly the workaround I'm looking for. Thanks!