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Using EEnet in SystemVerilog models

Robert Peruzzi

I'm not able to figure out how to use EEnet type in a SystemVerilog model. Objective is to have multiple cells driving and loading the same analog node.  So simple with Verilog-AMS, but so FAST using SystemVerilog once I get it to work ;-)

Here's some of the code:

`include "/tools/cadence/incisiv/IUS15.10_e035/tools.lnx86/affirma_ams/etc/dms/EE_pkg.sv"
import EE_pkg::*;

module <cell_name> (input <name>,

                                  input  var real <name>,

                                 ...

                                 output EEnet <output_name>  // This is one driver of the the multiply-driven, loaded nodel

                                );

...

endmodule

Save/Quit from editing the model calls the ncvlog compiler and produces this error message:


import EE_pkg::*;
            |
ncvlog: *E,NOPBIND (/proj/waters/workareas/bperuzzi/trunk/analog/waters_always_on/cds/waters_always_on/hiz_vddd_with_isolators/systemVerilog/verilog.sv,54|12): Package EE_pkg could not be bound.

More info:

nchelp ncvlog NOPBIND
nchelp: 14.20-s006: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
ncvlog/NOPBIND =
    No package of that name could be found.

The EE_pkg.sv is there and appears to be intact.  As far as I know, I'm the only one attempting to use it at my company.

I just received a suggestion to try compiling it with "irun filename.sv" and guess what?  It compiled without error.

Anybody know how to get it to compile using save/quit from the model editor within icfb?

Thanks,

Bob Peruzzi                            

  • In ADE, go to Simulation->Options->AMS Simulator.

    Add the EE_pkg.sv file to the "Files on run command line" which will pass the file to irun for compilation.

    Tim

  • Thanks for the suggestion, Tim. In the CIW and Library Manager I looked for but couldn't find an equivalent place to add that package. I want to compile as I save/quit from editing the model and not wait until the model and testbench are ready to run from ADE.

  • I'm not exactly sure of your use model. But you could add the following line at the top of your file: `include "<path to file.>/EE_pkg.sv" Tim

  • Tim,

    My use model is what I consider typical for icfb. Sequence of steps for a cell with an existing schematic and symbol:

    1. Library Mangager > File > New > Cell View ...

    Type: SystemVerilogText

      A starting point file opens up in my editor, including the module declaration and all inputs and outputs.


    2. For the analog inputs and outputs to be represented as real numbers I insert "var real" between "Input" and port name or between "output" and port name.


    3. I write the model code, save and quit the editor.  This calls ncvlog and checks for consistancy between cell views.  Users supposedly don't need to know what's under the hood when they save and quit ;-)

    What is different in this model is that one of the analog outputs is one of several models driving a node.  There are several models loading that node as well.  All trivial stuff in Verilog-AMS or Verilog-A, but it's a relatively new feature in SystemVerilog.  


    First attempt was to simply declare the node as advertised:

    output EEnet vddd

    One of my first tries was to place

    `include "<path to file.>/EE_pkg.sv"

    import EE_pkg::*;

    in the model file, before the module declaration.

    Save/quit (compile)  produces the error messages I posted. 

    However,

    irun <path to cellview>/systemVerilog.sv
    successfully compiles the model.

    Still seeking a solution.  I appreciate you sharing your ideas.

    Bob

  • Now I understand the issue. You're issue is with the Check & Save using ncvlog instead of irun. I thought you were trying to netlist.

    What version of Virtuoso are you using? I think there is a recent version where it will use 'irun' instead of 'ncvlog' but I need to verify. Meanwhile, a workaround is to use a `ifdef to "hide" the offending code and then use "-define" on the command line when you actually want to simulate.

    Tim

  • Virtuoso Design Environment version IC6.1.6-64b.500.6

    Cadence Library Manager version IC6.1.6-CAT33

    I'll try your `ifdef suggestion.

    Thanks!

    Bob Peruzzi

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