Using EEnet in SystemVerilog models

I'm not able to figure out how to use EEnet type in a SystemVerilog model. Objective is to have multiple cells driving and loading the same analog node.  So simple with Verilog-AMS, but so FAST using SystemVerilog once I get it to work ;-)

Here's some of the code:

`include "/tools/cadence/incisiv/IUS15.10_e035/tools.lnx86/affirma_ams/etc/dms/EE_pkg.sv"
import EE_pkg::*;

module <cell_name> (input <name>,

                                  input  var real <name>,

                                 ...

                                 output EEnet <output_name>  // This is one driver of the the multiply-driven, loaded nodel

                                );

...

endmodule

Save/Quit from editing the model calls the ncvlog compiler and produces this error message:

import EE_pkg::*;
            |
ncvlog: *E,NOPBIND (/proj/waters/workareas/bperuzzi/trunk/analog/waters_always_on/cds/waters_always_on/hiz_vddd_with_isolators/systemVerilog/verilog.sv,54|12): Package EE_pkg could not be bound.

More info:

nchelp ncvlog NOPBIND
nchelp: 14.20-s006: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
ncvlog/NOPBIND =
    No package of that name could be found.

The EE_pkg.sv is there and appears to be intact.  As far as I know, I'm the only one attempting to use it at my company.

I just received a suggestion to try compiling it with "irun filename.sv" and guess what?  It compiled without error.

Anybody know how to get it to compile using save/quit from the model editor within icfb?

Thanks,

Bob Peruzzi