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forcing signal to hierarchical connection in SystemVerilog when in interactive mode

Almendrico

Hi Cadence, all

I know it is possible to do hierarchical assigns/forces from the testbench. e.g:

assign clk   = chip_top.digital_core.some_clock;

I would like to do this kind of stuff from the ncsim interactive console. Can you please advice whether this is supported by ncsim and, if it is not, why ?

Thanks



  • First, you need to have "write" access turned on when you elaborate your design.

    irun -accesss w ...

    Then you can use the TCL commands "deposit" and "force" to put values on internal wires and variables in the design. Look them up in the docs to see how the commands differ and what their options are.

  • Hi TAM1,

    I should probably have explained better. I am familiar with what these commands do, and I am running with +rwc access. Problem is that ncsim does not like hierarchical references on the RHS of the assignment. I think it has to do with the fact that the hierarchical references are resolved at elaboration time, so they do not work in the TCL interactive console. Stuff like this can be done from the tcl console:

    force chip_top.digital_top.clk = 1'b0;

    But this does not work:

    force chip_top.digital_top.clk = tb.clk;

    (while it works if it is done inside an initial block in the testbench)

  • Well, this will do it. But it's really only a stop-gap. Coding the connection in the HDL will be much more efficient.

    stop -object top.sys_clk -exec {force top.t1.clk #top.sys_clk} -silent -continue

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