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compare VerilogA result with SystemVerilog result

NE555

Hi to everyone.

I made my circuit in verilogA with the code and circuit part. The simulation is very slow, so I made the systemverilog model.

Now I would compare the results. In some Cadence slide I saw that this is possible:

These are my results:

My question is: Was the image found in the Cadence slide a result of photoshop or is there a function in virtuoso or simvision to compare two results?

If is there this function, how it work?

Thank you very much

L.F.

Parents

  • Hi Luigi,


    I believe what you are seeing can be done by selecting two or more signals in the wavetrace, right-clicking on their names, then  "Create > Analog Overlay".

    You can even do this for digital signals when you set "Trace Type" to "Analog / ..." before.

    HTH

      Colin

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  • Hi Luigi,


    I believe what you are seeing can be done by selecting two or more signals in the wavetrace, right-clicking on their names, then  "Create > Analog Overlay".

    You can even do this for digital signals when you set "Trace Type" to "Analog / ..." before.

    HTH

      Colin

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