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Explicit wire declaration by Virtuoso netlister

stanzani

Hi all. 

When I generate a verilog netlist  out of virtuoso ncverilog netlister I see that  implicit net s(those internal to modules) are not esplicitly declared. Is there any way to force the netlister to explicitly  declare implicit wires. 

When implicit nets are multidimensional the netlister declare them. I think there's a way to force this behavior also for scalar wires.

 

Please help, 

thanks in advance.

- See more at: community.cadence.com/.../36386

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