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Including `defines with ncvlog netlisting

casparvv

All,

This is using IC6.1.7-64b.500.6. I have a mixed-signal hierarchy in which several of the blocks have both schematic and Verilog cellviews. The Verilog cellviews are purely digital representations of analog / mixed-signal circuit behavior. I'm using a file with some define statements to govern this behavior. For example, there is a module that does this:

    always @ (posedge in) begin
        #(`TIME_RUN_ADC);
        out = 1;
    end

in which TIME_RUN_ADC is defined elsewhere, in a file that gets included in the digital / ams simulations.

When I modify the code in the Cadence text editor and try to extract connectivity, it warns that the variable is not recognized (*E,NOTDIR). I've tried to edit the hdl.var to include -NOWARN NOTDIR, but then ncvlog reports that this error cannot be surpressed. I've also tried using -INCDIR to the directory that holds a file with the defines, but ncvlog still did not find them. Editing hdl.var to include -DEFINE TIME_RUN_ADC=xx works, but there are many different modeling constants throughout the chip that would produce a long list if defined in this way. Is there a way to pass a list of defines to ncvlog? Thanks in advance!

Best regards,

Caspar

Parents
  • Hi Steve,

    Thanks for your response. Perhaps I was unclear, the problem occurs after editing the code, not at compilation -- there I can include the 'defines.v' file and everything works fine (of course, during the sim, not having missing symbols is pretty important..). What I would like is a way to include the same 'define.v' with the process that extracts the Verilog from the text editor, i.e. when teSaveAndExtract() runs. So far, I've edited the hdl.var with some '-define AA=0' statements, but as you say, this is brute force and not scalable. My best bet was to use the -INCDIR statement in the same hdl.var, but that doesn't seem to work, or I'm not configuring it properly. Do you have any other ideas? Thanks!

    Caspar
Reply
  • Hi Steve,

    Thanks for your response. Perhaps I was unclear, the problem occurs after editing the code, not at compilation -- there I can include the 'defines.v' file and everything works fine (of course, during the sim, not having missing symbols is pretty important..). What I would like is a way to include the same 'define.v' with the process that extracts the Verilog from the text editor, i.e. when teSaveAndExtract() runs. So far, I've edited the hdl.var with some '-define AA=0' statements, but as you say, this is brute force and not scalable. My best bet was to use the -INCDIR statement in the same hdl.var, but that doesn't seem to work, or I'm not configuring it properly. Do you have any other ideas? Thanks!

    Caspar
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