#ifdef #else #endif inside module instantiation in Verilog

The problem is you've got a typo, it should be "#ifdef TRIAL" but you put "TRAIL". Only kidding ;-)

Your real problem is not the ifdef pragmas, it's the missing commas between the port connections.

Try this:

                         module tb_trail();

                              ....

                              test dut (

                                   .a(out),  // added a comma

                                   .b(in1) , // added a comma

                                #ifdef TRAIL

                                     .c(in3)   //no comma because it's the last one in the list

                                #else 

                                      .c(in4)

                                #endif 

                               );

Hi Stephen, 

       Thanks for typo correction. As I mentioned, "Please ignore my syntax errors". The original codes runs pages and pages, so i tried to mimic the concept into a smaller code version.  I do have commas placed in those areas, the main focus of the question is on the #ifdef #else #endif itself.  

      Does doing the instantiation with #ifdef PARAMETER works?  so far, i have never used or seen it before. 

Thanks!

Aarthy 

ifdef pragmas work everywhere; they are processed before any other syntax parsing and are independent of the Verilog code.

It's impossible to ignore syntax errors when you're asking about a parser problem, so either provide us with a runnable example of your issue, or at least clean up the other errors so that we only look at the one you think is real.

I'm 100% certain that your issue has nothing to do with the ifdef/else/endif, it's far more likely that you've simply broken your original code by putting the ifdef in a way that either the true or false branch introduces a syntax error by, for example, having a comma in one branch and not in the other. You'll get a much quicker solution if you can share the full code either here or by filing a support request at support.cadence.com (better, if the code is confidential).

It looks like the person who created your Verilog example was using the C preprocessor to handle his defines and macros. Your example shows #ifdef which will work for C. The Verilog preprocessor uses the "accent-grave" character or backwards-single-quote `. It is in the far upper-left of my keyboard. Try this:

`ifdef TRIAL

  .c(in3),

`else

  .c(in4),

`endif

Good catch Tom, I've been writing C code all day and totally missed the # versus back-tick typo!

As ever though, this highlights why it's better to submit a runnable testcase rather than a broken code fragment that has multiple errors in it!

Hi Stephen, 

          I totally understand. It is my mistake :( I will make sure I will post a bug free/no syntax error codes in future. The code is based on open source License, so I wasn't sure whether I can just like post anywhere.  I should have checked before posting my example.  :(

Tom, Thanks for your response. I will change and try to simulate, will update here. 

Thanks!

Aarthy

Hi Tom,

   Changing the " # " to " ` " does solve that missing parenthesis error.

   Thank you!