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  3. Is ncsim (version 12.10-s19) fully compatible with VHDL...

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Is ncsim (version 12.10-s19) fully compatible with VHDL2008

pyohayo
pyohayo over 6 years ago

Hello,

When compiling VHDL source with option -V200X, I get error on this line:

pixel_new := (others=>'0') when lfsr_val(15) else (others=>'1');

Any comments.

Thanks.

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  • StephenH
    StephenH over 6 years ago

    Firstly, Incisive 12.10 is extremely old and out of maintenance, it was released 7 years ago. You really should move to something that is supported; either the newer Xcelium platform, or if you have to stick to Incisive then at least use the 15.20 version which is the last of the Incisive versions and only has a 4 year old feature set.

    Secondly, you haven't said what the error message was, so it's impossible to comment intelligently on the single line of code you're quoting. Please supply a small runnable example so that we can reproduce the error.

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  • pyohayo
    pyohayo over 6 years ago in reply to StephenH

    Thanks. Here is screenshot of compilation results

    link to image

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  • pyohayo
    pyohayo over 6 years ago in reply to StephenH

    Thanks. Here is screenshot of compilation results

    link to image

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  • StephenH
    StephenH over 6 years ago in reply to pyohayo

    Well, I had to guess at your data types, so this example might not be fully representative:

    library ieee;
    use ieee.std_logic_1164.all;
    entity dut is
    end entity;
    architecture rtl of dut is
    signal lfsr_val : std_logic_vector (15 downto 0);
    begin
    p : process
    variable pixel_new : std_logic_vector (7 downto 0);
    begin
    pixel_new := (others=>'0') when lfsr_val(15)='1' else (others=>'1');
    end process;
    end rtl;

    Even in Incisive 15.20 this produces the same error that you showed in your screenshot, however I can tell you that this compiles fine in Xcelium, so you should look to switch to that really.

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  • pyohayo
    pyohayo over 6 years ago in reply to StephenH

    Thanks Stephen,

    Does it mean that my original guess was true ... i.e. ncim doesn't (at least fully) support VHDL2008 ?

    After all my version date 2013 ...

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  • StephenH
    StephenH over 6 years ago in reply to pyohayo

    In general, language support is added incrementally, generally prioritised by customer demand. There is very little demand for VHDL at all, so most R&D effort goes into implementing SystemVerilog features (there have been 3 major SV revisions since 2008). In an ideal world we would have the time and money to implement every language feature for all languages, but in reality that isn't possible so R&D has to focus on the most needed features. In fact there are many aspects of VHDL and SV that are in the standard but in reality aren't useful so don't get requested or implemented!

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  • pyohayo
    pyohayo over 6 years ago in reply to StephenH

    So, 2008 is partially supported ?

    If it's the case, does exist somewhere a list of features 2008, that are not supported?

    Thanks.

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  • StephenH
    StephenH over 6 years ago in reply to pyohayo

    I don't think we even have the docs for 12.10 online these days, the nearest I can find is for 15.20 (itself 4 years old). https://support.cadence.com/apex/techpubDocViewerPage?xmlName=vhdlmodeling.xml&title=VHDL:%20Modeling%20Your%20Hardware%20--%20Modeling%20Your%20Hardware%20-%201.1%20%20IEEE%201076-1993%20Features&hash=v93_features&c_version=15.2&path=VHDLModeling/VHDLModeling15.2/modeling.html#v93_features

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