probe tcl syntax to save variables inside automatic tasks in systemverilog

Hi Dimitar, I have the same issue , cant probe variables inside a automatic task.

Anyone can help us with this?

The problem is that automatic tasks and functions are transient, so they don't have an associated hierarchy in the way that a static function or task does. With static methods, the internal variables are shared across all calls to the method and the variables exist "forever", hence like any module-scoped signal, they have a true hierarchical name and can be probed.

With an automatic task or function, the variables are existing only whilst that method is executing, they are dynamically allocated on the "heap" memory and are discarded when the method finishes. Given that an automatic task could have multiple parallel threads of execution (i.e. the task might have been started multiple times in parallel before any one copy has completed), then the only way to uniquely identify the actual set of variables for *that* instance of the task, would be to invent some kind of automatic naming that is based on the execution stack and unique across the life of the simulation (to avoid name clashes or ambiguity if a name got reused later). If you had 1000 calls to the task, that would need 1000 unique names in the hierarchy, and it would get very cluttered.

On top of that, since the variables only exist whilst the method is running, and a method may complete in zero simulation time, how would that even be shown on the waveform?

This is why you can't probe variables inside automatic methods - there's no good way to view the results! If you need to debug inside automatic methods, it's best to place breakpoints in the method and debug interactively.

If you know you're only going to have 1 copy of the task running at once, consider making it static, or declare some static variables to assign debug information to (remember, an automatic method is permitted to access static variables).