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probe tcl syntax to save variables inside automatic tasks in systemverilog

dtodorov

Greetings,

I am running a testbench via xcellium, where the signals to be probed are defined via probe.tcl file, containing :

probe -create -tasks -functions -all -depth 4 -dynamic -variables testbench

However, inside the testbench I have an automatic SystemVerilog task, which internal variables I need to save. In Simvision, I see the task listed as a hierarchy member, but the internal variables are not saved. 

Variables in all other tasks (not automatic tasks) are saved as expected.

I searched through xcellium documentation for tcl commands, specifically in the probe definition, but could not figure out what is missing in the arguments I use. 

Has anybody encountered such hiccup so far?

Thanks,

Dimitar

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  • Pedro P

    Hi Dimitar, I have the same issue , cant probe variables inside a automatic task.

    Anyone can help us with this?

Reply
  • Pedro P

    Hi Dimitar, I have the same issue , cant probe variables inside a automatic task.

    Anyone can help us with this?

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