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Xcelium: Link a third-party library to your simulation

Anas2023a95

Dear all, 


I have a VHDL digital design that I want to synthesise and simulate using TSMC180n Tech. 
I have successfully generated the netlists based on the TSMC tech using Cadence Genus (reads .vhd and generates .v netlists).
When I want to simulate the generated netlists, I have the following error message reported tens of times:

"xmelab: *E,CUVMUR (./Clk_Divider_m.v,12|26): instance ':Clk_Divider_tb(bench):uut@Clk_Divider<module>.RC_CG_HIER_INST0@RC_CG_MOD<module>.RC_CGIC_INST' of design unit 'CKLNQD1BWP7T' is unresolved in 'worklib.RC_CG_MOD:v'. INVD0BWP7T g300(.I (reset), .ZN (n_32));"

I'm assuming that the simulator cannot find the definitions of the cells (mentioned in the netlist) in its library.

My question is: How do I correctly link the .lib file of the TSMC tech so that Xcelium can resolve those cells?

Many thanks

Anas

  • The simulator needs Verilog (or VHDL) models of the cells; the *.lib files from synthesis are not used for simulation.

    You'll need to look in your TSMC package to find the relevant cell models. These would typically be added to the xrun command using either the -y (for a library directory containing lots of files where each file represents one cell) or -v (where all the cells are in a single file that you pass as the argument to -v).

    e.g.

    xrun -y /path/to/cell_lib_dir/ <other args>

    or

    xrun -v /path/to/cells.v <other args>

  • in reply to StephenH

    Hello Stephen!

    Thank you very much for your reply! It is very helpful!

    I have managed to find the .v file in the PDK and feed it to the simulator as you described. 
    However, another error is now shown. 

    xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.
    xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 2), exiting.

    It says (just before the error message) that two modules have the timescale unset. Is this related to the shown error?

    I have attached the log file below if you would like to check it for more info. It reports lots of warnings about unconnected ports, but I think this should not cause the simulation to terminate. 

    Thank you very much!

    Anas

    xrun: 22.03-s005: (c) Copyright 1995-2022 Cadence Design Systems, Inc.
    TOOL: xrun 22.03-s005: Started on Feb 10, 2023 at 12:19:19 GMT
    xrun
    Clk_Divider_m.v
    Clk_Divider_tb.vhd
    -top Clk_Divider_tb
    -v /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v
    -access -rwc
    file: Clk_Divider_m.v
    module worklib.RC_CG_MOD:v
    errors: 0, warnings: 0
    module worklib.Clk_Divider:v
    errors: 0, warnings: 0
    file: /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v
    module tcb018gbwp7t.CKAN2D0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.CKLNQD1BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.DFCND0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.DFCNQD1BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.EDFCND1BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.HA1D0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.IIND4D0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.IND2D0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.IND3D0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.INR2D0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.INR4D0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.INVD0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.NR3D0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.NR4D0BWP7T:v
    errors: 0, warnings: 0
    module tcb018gbwp7t.XNR2D1BWP7T:v
    errors: 0, warnings: 0
    primitive tcb018gbwp7t.tsmc_dla:v
    errors: 0, warnings: 0
    primitive tcb018gbwp7t.tsmc_xbuf:v
    errors: 0, warnings: 0
    primitive tcb018gbwp7t.tsmc_mux:v
    errors: 0, warnings: 0
    primitive tcb018gbwp7t.tsmc_dff:v
    errors: 0, warnings: 0
    Clk_Divider_tb.vhd:
    errors: 0, warnings: 0
    WORKLIB.CLK_DIVIDER_TB (entity):
    streams: 1, words: 38
    WORKLIB.CLK_DIVIDER_TB:BENCH (architecture):
    streams: 1, words: 214
    xmelab: *W,ARCMRA: Elaborating the WORKLIB.CLK_DIVIDER_TB:BENCH, MRA (most recently analyzed) architecture.
    Elaborating the design hierarchy:
    xmelab: *W,CUDEFB: default binding occurred for component instance (:Clk_Divider_tb(bench):uut) with verilog module (worklib.Clk_Divider:v).
    Caching library 'tcb018gbwp7t' ....... Done
    CKLNQD1BWP7T RC_CGIC_INST(.E (enable), .CP (ck_in), .TE (test), .Q
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,12|26): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,4107): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,4107): VSS

    INVD0BWP7T g300(.I (reset), .ZN (n_32));
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,29|16): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10746): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10746): VSS

    IND2D0BWP7T g461__2398(.A1 (Divider_count[0]), .B1 (n_36), .ZN
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,30|23): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10368): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10368): VSS

    IIND4D0BWP7T g462__5107(.A1 (n_31), .A2 (Divider_count[0]), .B1
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,32|24): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10260): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10260): VSS

    IND3D0BWP7T g463__6260(.A1 (Divider_count[12]), .B1 (n_30), .B2
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,34|23): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10428): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10428): VSS

    NR3D0BWP7T g464__4319(.A1 (Divider_count[6]), .A2 (Divider_count[4]),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,36|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,15010): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,15010): VSS

    INR4D0BWP7T g465__8428(.A1 (Divider_count[3]), .B1
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,38|23): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10695): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10695): VSS

    NR4D0BWP7T g466__5526(.A1 (Divider_count[5]), .A2 (Divider_count[7]),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,41|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,15085): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,15085): VSS

    DFCNQD1BWP7T \Divider_count_reg[12] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,43|37): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g471__6783(.A (n_24), .B (Divider_count[12]), .CO (n_26),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,45|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[11] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,47|37): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g473__3680(.A (n_22), .B (Divider_count[11]), .CO (n_24),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,49|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[10] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,51|37): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g475__1617(.A (n_20), .B (Divider_count[10]), .CO (n_22),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,53|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[9] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,55|36): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g477__2802(.A (n_18), .B (Divider_count[9]), .CO (n_20),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,57|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[8] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,59|36): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g479__1705(.A (n_16), .B (Divider_count[8]), .CO (n_18),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,61|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[7] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,63|36): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g481__5122(.A (n_14), .B (Divider_count[7]), .CO (n_16),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,65|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[6] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,67|36): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g483__8246(.A (n_12), .B (Divider_count[6]), .CO (n_14),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,69|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[5] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,71|36): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g485__7098(.A (n_10), .B (Divider_count[5]), .CO (n_12),
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,73|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[4] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,75|36): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g487__6131(.A (n_7), .B (Divider_count[4]), .CO (n_10), .S
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,77|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[3] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,79|36): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    CKAN2D0BWP7T g489__1881(.A1 (n_8), .A2 (n_36), .Z (n_9));
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,81|24): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,3550): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,3550): VSS

    HA1D0BWP7T g490__5115(.A (n_5), .B (Divider_count[3]), .CO (n_7), .S
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,82|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T \Divider_count_reg[2] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,84|36): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    HA1D0BWP7T g492__7482(.A (n_2), .B (Divider_count[2]), .CO (n_5), .S
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,86|22): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,9981): VSS

    DFCNQD1BWP7T ADC_clko_reg(.CDN (n_32), .CP (clk_200M), .D (n_4), .Q
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,88|26): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    DFCNQD1BWP7T \Divider_count_reg[0] (.CDN (n_32), .CP (clk_200M), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,90|36): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,5233): VSS

    XNR2D1BWP7T g495__4733(.A1 (n_36), .A2 (clk_16k), .ZN (n_4));
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,92|23): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,25632): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,25632): VSS

    INR2D0BWP7T g497__6161(.A1 (n_36), .B1 (Divider_count[0]), .ZN (n_3));
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,93|23): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10527): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10527): VSS

    INR2D0BWP7T g498__9315(.A1 (Divider_count[0]), .B1 (n_1), .ZN (n_2));
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,94|23): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10527): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,10527): VSS

    DFCND0BWP7T \Divider_count_reg[1] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,95|35): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,4978): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,4978): VSS

    EDFCND1BWP7T \Divider_count_reg[13] (.CDN (n_32), .CP (rc_gclk), .D
    |
    xmelab: *W,CUVWSB (./Clk_Divider_m.v,97|37): 2 inout ports were not connected:
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,7696): VDD
    xmelab: (/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/verilog/tcb018gbwp7t_270a/tcb018gbwp7t.v,7696): VSS

    Top level design units:
    :clk_divider_tb(bench):
    Modules w/wo timescales:
    timescale of worklib.RC_CG_MOD:v = NOTSET
    timescale of worklib.Clk_Divider:v = NOTSET
    timescale of tcb018gbwp7t.XNR2D1BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.NR4D0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.NR3D0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.INVD0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.INR4D0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.INR2D0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.IND3D0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.IND2D0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.IIND4D0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.HA1D0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.EDFCND1BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.DFCNQD1BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.DFCND0BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.CKLNQD1BWP7T:v = 1ns/1ps
    timescale of tcb018gbwp7t.CKAN2D0BWP7T:v = 1ns/1ps
    xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.
    xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 2), exiting.
    TOOL: xrun 22.03-s005: Exiting on Feb 10, 2023 at 12:19:19 GMT (total: 00:00:00)

  • in reply to StephenH

    Hello Stephen!

    Thank you very much for your reply! It is very helpful!

    I have managed to find the .v file in the PDK and feed it to the simulator as you described. 
    However, another error is now shown. 

    xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.
    xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 2), exiting.

    It says (just before the error message) that two modules have the timescale unset. Is this related to the shown error?

    I have attached the log file below if you would like to check it for more info. It reports lots of warnings about unconnected ports, but I think this should not cause the simulation to terminate. 

    Thank you very much!

    Anas

  • in reply to Anas2023a95

    Verilog requires that if any one module uses a timescale, all modules must also use timescale. The simplest option is to add "-timescale 1ns/1ps" to the xrun command, but make sure the time precision (1ps in my example) is suitable for the precision needed in your simulation

  • in reply to StephenH

    You are super helpful, Stephen! 

    Thank you so much! 

  • in reply to StephenH

    Sorry Stephen, one more thing, please. 

    The simulation runs now but it freezes, any idea why it would be the case? 
    My testbench is very simple and has already been tested on Xilinx Vivado. 



    Thank you very much!
    Anas

  • in reply to Anas2023a95

    There are many potential causes of a hang, often it's a zero-delay loop somewhere. This app note gives some hints for debugging: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTGDEA2&pageName=ArticleContent

  • in reply to StephenH

    Hello Stephen, 

    Thank you for your reply! 
    I tried most of the hints in the provided link and still experiencing the same problem (shown in the previous image).

    My testbench is already simulated in Xilinx Vivado and it runs fine. 

    Any other ways to check it out? 

    Many thanks,

    Anas

  • in reply to Anas2023a95

    I think it is running fine, but it doesn't finish until I stop it by (Ctlr+z). 

    Thanks for your help, Stephen! 

  • in reply to Anas2023a95

    Ctrl-Z just suspends the process. You need Ctrl-C to interrupt the simulator (at which point it will tell you the current simulation time).

    Bear in mind that different simulators can have different behaviours, so just because your code runs in one tool, doesn't mean that it's going to work in any other tool. I'm not an expert on Xilinx Vivado, but my understanding is that it wraps around the main commercial logic simulators including Xcelium, and it may be giving the simulator certain options to help it simulate the Xilinx libraries correctly. 

    Since you already have a proejct set up in Vivado, maybe you can look to see if there's an option in Vivado to simulate with Xcelium, so that you don't need to write your own script to compile the design. This might then get you better results.

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