Xcelium: Link a third-party library to your simulation

The simulator needs Verilog (or VHDL) models of the cells; the *.lib files from synthesis are not used for simulation.

You'll need to look in your TSMC package to find the relevant cell models. These would typically be added to the xrun command using either the -y (for a library directory containing lots of files where each file represents one cell) or -v (where all the cells are in a single file that you pass as the argument to -v).

e.g.

xrun -y /path/to/cell_lib_dir/ <other args>

or

xrun -v /path/to/cells.v <other args>

Hello Stephen!

Thank you very much for your reply! It is very helpful!

I have managed to find the .v file in the PDK and feed it to the simulator as you described. 
However, another error is now shown. 

xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.
xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 2), exiting.

It says (just before the error message) that two modules have the timescale unset. Is this related to the shown error?

I have attached the log file below if you would like to check it for more info. It reports lots of warnings about unconnected ports, but I think this should not cause the simulation to terminate. 

Thank you very much!

Anas

Verilog requires that if any one module uses a timescale, all modules must also use timescale. The simplest option is to add "-timescale 1ns/1ps" to the xrun command, but make sure the time precision (1ps in my example) is suitable for the precision needed in your simulation

Verilog requires that if any one module uses a timescale, all modules must also use timescale. The simplest option is to add "-timescale 1ns/1ps" to the xrun command, but make sure the time precision (1ps in my example) is suitable for the precision needed in your simulation

You are super helpful, Stephen! 

Thank you so much! 

Sorry Stephen, one more thing, please. 

The simulation runs now but it freezes, any idea why it would be the case? 
My testbench is very simple and has already been tested on Xilinx Vivado. 



Thank you very much!
Anas

There are many potential causes of a hang, often it's a zero-delay loop somewhere. This app note gives some hints for debugging: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTGDEA2&pageName=ArticleContent

Hello Stephen, 

Thank you for your reply! 
I tried most of the hints in the provided link and still experiencing the same problem (shown in the previous image).

My testbench is already simulated in Xilinx Vivado and it runs fine. 

Any other ways to check it out? 

Many thanks,

Anas

I think it is running fine, but it doesn't finish until I stop it by (Ctlr+z). 

Thanks for your help, Stephen! 

Ctrl-Z just suspends the process. You need Ctrl-C to interrupt the simulator (at which point it will tell you the current simulation time).

Bear in mind that different simulators can have different behaviours, so just because your code runs in one tool, doesn't mean that it's going to work in any other tool. I'm not an expert on Xilinx Vivado, but my understanding is that it wraps around the main commercial logic simulators including Xcelium, and it may be giving the simulator certain options to help it simulate the Xilinx libraries correctly. 

Since you already have a proejct set up in Vivado, maybe you can look to see if there's an option in Vivado to simulate with Xcelium, so that you don't need to write your own script to compile the design. This might then get you better results.