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how to force the variables inside a class? i'm facing this error "FOAUTO"

My intention is to force variables inside a class of type uvm_component. But as I cannot show that confidential code, i'm trying to replicate a similar code.

Here i'm able to force the variable j inside the module main but unable to do a force on the variable num which is inside class example.

i tried to change the scope, but the simulator always throws "*E,FOAUTO: Invalid way of setting automatic variable:"

what is a valid way to force the variables inside the class. I've read the document on the force, but it mentions about verilog/vhdl objects.

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tpylant over 1 year ago

Can you show how you're trying to force obj.num and monitoring the value of obj.num?
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chetan somana over 1 year ago in reply to tpylant

I have shown how im forcing the module variable and class variable. Not sure if I had answered the later question.

My original test has many nested blocked inside a case and endcase block; My intention is to save time by forcing desired value of the case so I can just resimulate using reset instead of complile and simulate.
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tpylant over 1 year ago in reply to chetan somana

I had to make num a static variable to be able to force it.

class example;
static rand int num;
endclass
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StephenH over 1 year ago in reply to tpylant

xcelium> force ci.b = 1

xmsim: *E,FOAUTO: Invalid way of setting automatic variable: m.ci.b.

Extended help:

% xmhelp xmsim FOAUTO

xmhelp: 24.01-a071: (c) Copyright 1995-2024 Cadence Design Systems, Inc.

xmsim/FOAUTO =

 A force, release or delayed deposit command cannot be used on

 an automatic variable.  Automatic variables are Verilog variables

 declared in a class, automatic task or function.

 (Default severity: 'E')

chetan somana over 1 year ago in reply to tpylant

Now I can force on the static variables used in the verification environment.
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chetan somana over 1 year ago in reply to tpylant

Now I can force on the static variables used in the verification environment.
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