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Can I force or probe a signal in vhdl module from verilog top testbench?

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At 2/07/2007 10:01 AM a message was posted to a thread you were tracking. -- RE: Using the Forum by hubertx

Can I force or probe a signal in vhdl module from verilog top testbench?
I heard some simulator has its own way to do that easily, can you give me a example code to do that with ncsim?


Originally posted in cdnusers.org by foster
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