for/generate

Hi,
I am currently studying psl and having some doubts. I have done a simple edge detector to starting using psl, this is the edge detector:


module edge_detector(sign_i, // Input of the Edge Detector
             rise_o, // Rising Edge Output of the Edge Detector
             fall_o, // Falling Edge Output of the Edge Detector
             clk, // clock
             rst_b, // Synchronous Reset
             );
  
//--------------------- Parameters Declaration ---------------------------------
   parameter SIZE = 1;
       
//-------------------- Inputs Declaration --------------------------------------
   input [SIZE-1:0]sign_i;
   input clk;
   input rst_b;
  
   
//---------------------- Outputs Declaration -----------------------------------
   output [SIZE-1:0]rise_o;
   output [SIZE-1:0]fall_o;

//------------------- Types Declaration ----------------------------------------
   wire       clk;
   wire       rst_b;
   wire [SIZE-1:0]sign_i;
   wire [SIZE-1:0]rise_o;
   wire [SIZE-1:0]fall_o;
   reg  [SIZE-1:0]sign_i_syn;
   reg  [SIZE-1:0]out_ff2;
   wire [SIZE-1:0]out_xor;

   genvar i; // auxiliar variable to generate
   
 generate for(i=0;i
   begin
//------------------------ Sequential Part ------------------------------------
  
   always @(posedge clk)
     begin
       if (!rst_b)
     begin
       
            sign_i_syn[i]
     
     end //if(!rst)  
      
       else 
     begin
      
        sign_i_syn[i]
           //Transform the entering signal in synchronous
          
        out_ff2 [i]
        //Update the second ff output value
        
     end //else
     end //always @(posedge clk)


//-------------------------------- Combinational Part ------------------------

   assign out_xor[i] = (sign_i_syn[i] ^ out_ff2[i]);
// keeps the output from the xor in 1 for 1 period of clock in the rise or fall
 
   assign rise_o[i] = (sign_i_syn[i] & out_xor[i]);
// if the entering sinal has high level and the pulse in the xor output
   // represents a rising edge
       
   assign  fall_o[i] = ~(sign_i_syn[i] | ~out_xor[i]);
// if the entering sinal has low level and the pulse in the xor output
   // represents a falling edge
    
   end // for (generate) 
 endgenerate
 

As can be seing above it is sizeble by parameter. So I have tried to also make sizeble psl.
In the psl introduction from cadence I have found this option:



for i in {0,1,2} generate
begin: check1
    {// psl check_init: assert (!value[i]) @rose(resetn);
end
endgenerate;

So I have tried this:

for i in {0,1,2} generate
begin: check1
{//psl RISING: assert always ( rose(sign_i[0]) -> next PULSE(rise_o)
// abort !rst_b)
// report "Rising Edge Failed " severity warning;
//@fell(clk);
end
endgenerate;


And I had this bunch of errors:
for i in {0,1,2} generate
|
ncvlog: *E,EXPLPA (EdgeDetector.v,122|4): expecting a left parenthesis ('(') [12.1.3(IEEE 2001)].
{//psl RISING: assert always ( rose(sign_i[0]) -> next PULSE(rise_o)
|
ncvlog: *E,EXPEND (EdgeDetector.v,124|4): Expecting the keyword 'end' [12.1.3(IEEE 2001)].
{//psl RISING: assert always ( rose(sign_i[0]) -> next PULSE(rise_o)
|
ncvlog: *E,NOTSTT (EdgeDetector.v,124|33): expecting a statement [9(IEEE)].
{//psl RISING: assert always ( rose(sign_i[0]) -> next PULSE(rise_o)
|
ncvlog: *E,EXPSMC (EdgeDetector.v,124|52): expecting a semicolon (';') [10.2.2][10.2(IEEE)].
{//psl RISING: assert always ( rose(sign_i[0]) -> next PULSE(rise_o)
|
ncvlog: *E,EXPSMC (EdgeDetector.v,124|63): expecting a semicolon (';') [9.7.3(IEEE)].
{//psl RISING: assert always ( rose(sign_i[0]) -> next PULSE(rise_o)
|
ncvlog: *E,EXPSMC (EdgeDetector.v,124|64): expecting a semicolon (';') [9.7.3(IEEE)].
{//psl RISING: assert always ( rose(sign_i[0]) -> next PULSE(rise_o)
|
ncvlog: *E,EXPSMC (EdgeDetector.v,124|71): expecting a semicolon (';') [9.7.3(IEEE)].
endgenerate;
|

My next try was to use the regular generate form in verilog:

generate for(i=0;i
begin: Rise
//psl RISING: assert always ( rose(sign_i[0]) -> next PULSE(rise_o)
// abort !rst_b)
// report "Rising Edge Failed " severity warning;
//@fell(clk);
end
endgenerate

It really worked, but the probes did not worked!! They are set like this:

probe -create -assertions -transaction -waveform -name RISING edge_detector_tb.edge_detector.Rise[0].RISING


The log result is:
ncsim> probe -create -assertions -transaction -waveform -name RISING edge_detector_tb.edge_detector.Rise[0].RISING
Created probe RISING


Even in the assertion browser, when I click in the assertion and put type transaction it do not appers in the SimVision. It shows no error, only doesn't apper.

Could somebody show me the best way of doing this and explain me why this ways did not work?

Thanks,

Originally posted in cdnusers.org by alexsieh