Stats

  • Locked Locked
  • Replies 1
  • Subscribers 64
  • Views 5718
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Calculating Throughput & hence Band-width

archive

Hi Guys,
Wanted to calculate the throughput in case of accessing memory.If consecutive write & reads are ther how we can prove that so and so throughput is achieved.need to consider the total time taken for access or how?
Thanks.


Originally posted in cdnusers.org by vlsi_dude
Parents

  • Hello:

    You may consider use several cover statements to time the memory access latency using formal analysis. Take single read as an example: we can roughly guess the read latency using following cover properties in SVA and then run formal analysis:

    cover_rd_latency_2: cover property (@(posedge clk) read_en ##2 read_vld); (Fail)
    cover_rd_latency_3: cover property (@(posedge clk) read_en ##3 read_vld); (Pass)
    cover_rd_latency_4: cover property (@(posedge clk) read_en ##4 read_vld); (Fail)

    In the above example, we can find single memory read latency is 3 cycles.

    We can apply the same technique to time the memory latency/bandwidth for different combinations of consecutive read/write commands.

    Hope this helps,
    Darrow


    Originally posted in cdnusers.org by darrowchu
Reply

  • Hello:

    You may consider use several cover statements to time the memory access latency using formal analysis. Take single read as an example: we can roughly guess the read latency using following cover properties in SVA and then run formal analysis:

    cover_rd_latency_2: cover property (@(posedge clk) read_en ##2 read_vld); (Fail)
    cover_rd_latency_3: cover property (@(posedge clk) read_en ##3 read_vld); (Pass)
    cover_rd_latency_4: cover property (@(posedge clk) read_en ##4 read_vld); (Fail)

    In the above example, we can find single memory read latency is 3 cycles.

    We can apply the same technique to time the memory latency/bandwidth for different combinations of consecutive read/write commands.

    Hope this helps,
    Darrow


    Originally posted in cdnusers.org by darrowchu
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.