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System verilog and System C

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is there any resource showing how to write a verification environmentment mixing Sytem verilog and System C? A complex application example would be great

Cheers


Originally posted in cdnusers.org by marco.stanzani
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    Hi,
    As far as I can read from LRM, class is not allowed through DPI, but I can see that to be a very good value addition. Is there an enhancement to IEEE 1800 on this? BTW, will NC support class sharing across SV and SystemC?

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
Reply
  • archive

    Hi,
    As far as I can read from LRM, class is not allowed through DPI, but I can see that to be a very good value addition. Is there an enhancement to IEEE 1800 on this? BTW, will NC support class sharing across SV and SystemC?

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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