Constraints, randomize bits in a vector

I want to randomly set a weighted random number of bits in a vector.

The code below randomizes the number of bits that are set based on the weights provided, but I haven't figured out how to insert the weighted random number of bits randomly in a vector.

I have some code commented out that was an idea I had, which may be wrong, but functions in constraints doesn't seem to be supported.

I'm using IUS5.6-s2. Thanks.

To run: ncverilog sv_test.v +sv

module sv_test();
class constraints;
bit [31:0] bit_vector;
rand bit [31:0] bit_vector_rand;
rand bit [5:0] count;

constraint c0 {
count dist { [1:5]:/40,[6:25]:/20,[26:31]:/40 };
}

function int count_ones ( input bit [5:0] w );
for( count_ones = 0; w != 0; w = w >> 1 )
count_ones += w & 1'b1;
endfunction

// constraint c1 {
// count==count_ones(bit_vector_rand);
// }

function void post_randomize();
bit_vector = {{32{1'b1}},{32{1'b0}}} >> (32-count);
$display("%d",count);
$display("x%h",bit_vector);
// $display("x%h",bit_vector_rand);
endfunction

endclass

constraints a = new;

integer num_iterations;

integer seed;
initial begin
num_iterations = 10;
if ($value$plusargs("SEED=%d",seed)) begin
$display("Using SEED=%d", seed);
end else begin
$display("Using default seed");
end
process::self.srandom(seed);
for (int i = 0; i
if ( a.randomize() == 0 ) begin
$display("%d error!",i);
end
end
end
endmodule