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Calling VHDL procedures in SystemVerilog Testbench.

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Is there a way to call VHDL procedures in a SV TB without translating them into SV tasks.. ?


Originally posted in cdnusers.org by mirzani
Parents

  • Mayank,
          To call a task from within a class, one can go via virtual interface:

      interface my_if;
         task my_task;
     //

      class my_c;
        virtual my_if my_if_0;

        task call_task();
           my_if_0.my_task;

    However I've seen tools not fully supporting this yet/premamture support. Till then you are better off with a WA like:

      interface my_if;
         task my_task; endtask


         always @my_trigger begin
             my_task;
         end

    Then trigger this "my_trigger" from within the class.

    This was skeleton code, if you have more problems, show us full code or send it to me via email (ajeetha <> gmail), I will see if I can help.

    HTH
    Ajeetha, CVC
    www.noveldv.com  


    Originally posted in cdnusers.org by ajeetha
Reply

  • Mayank,
          To call a task from within a class, one can go via virtual interface:

      interface my_if;
         task my_task;
     //

      class my_c;
        virtual my_if my_if_0;

        task call_task();
           my_if_0.my_task;

    However I've seen tools not fully supporting this yet/premamture support. Till then you are better off with a WA like:

      interface my_if;
         task my_task; endtask


         always @my_trigger begin
             my_task;
         end

    Then trigger this "my_trigger" from within the class.

    This was skeleton code, if you have more problems, show us full code or send it to me via email (ajeetha <> gmail), I will see if I can help.

    HTH
    Ajeetha, CVC
    www.noveldv.com  


    Originally posted in cdnusers.org by ajeetha
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