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  3. Calling VHDL procedures in SystemVerilog Testbench.

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Calling VHDL procedures in SystemVerilog Testbench.

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archive over 18 years ago

Is there a way to call VHDL procedures in a SV TB without translating them into SV tasks.. ?


Originally posted in cdnusers.org by mirzani
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    archive over 18 years ago

    Hi Mirzani.

    Hierarchical references to VHDL are not supported yet. I believe this is due to restrictions in the VHDL specification.
    I've been told this will change in the next version of VHDL, but I don't know any more than that.

    Steve.


    Originally posted in cdnusers.org by stephenh
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    archive over 18 years ago

    I should have used the word 'import' instead of call .
    I was wondering if there is an equivalent hdl_task(VERA) to import the VHDL procedures placed in a separate package..


    Originally posted in cdnusers.org by mirzani
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    archive over 18 years ago

    Though not in LRM, in principle SV DPI can be extended for this. But why wait? I've been doing this for several years now with little WA. Pseudo-code:

    VHDL
    =======
    procedure vhdl_proc;...

    entity dummy (call_vhdl_proc : in bit)
    ...

    arch..
      process (call_vhdl_proc)
         vhdl_proc

    Verilog
    --------

    // Instantiate the dummy VHDL, toggle the "call_vhdl_proc"
       
    HTH
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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    archive over 18 years ago

    Hi,  I would also like to know if there is a way to map verilog tasks to system verilog tasks. Trying to build sys verilog wrappers around verilog tasks


    Originally posted in cdnusers.org by DM
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    archive over 18 years ago

    Posted By DM on 3/05/2007 6:28 PM
    Hi,  I would also like to know if there is a way to map verilog tasks to system verilog tasks. Trying to build sys verilog wrappers around verilog tasks

    Hi DM,
          You don't really need any mapping - SV is on top of Verilog and is 100% backward compatible and hence this mapping is not necessary.

    What exactly are your trying to do? Reuse module based tasks inside class based env? That will be little tricky and require some coding effort. Give us more details, we can suggest.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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    archive over 18 years ago

    Hi, Thanks for the reply. We'll be having a verification environment which includes basic verilog tasks. The upper level sys verilog TB will have to make use of these tasks. So how can I refer to these verilog tasks from sys verilog. Does importing help? or shud we wrap the verilog tasks & use something similar to hdl_task as in Vera??


    Originally posted in cdnusers.org by DM
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    archive over 18 years ago

    Yes Same problem I am facing. I need to call [b] Verilog tasks defined in a module <> hierarchy [/b], from my [b] classes in SystemVerilog [/b].
    How can it be made possible ??

    even defining them as extern task<> in SystemVerilog, it's giving compile time error, saying no module defined.

    Is there any way to call them through Interface definition etc..??

    Regards
    Mayank


    Originally posted in cdnusers.org by mayank
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    archive over 18 years ago

    Yes Same problem I am facing. I need to call Verilog tasks defined in a module <> hierarchy , from my classes in SystemVerilog .
    How can it be made possible ??

    even defining them as extern task<> in SystemVerilog, it's giving compile time error, saying no module defined.

    Is there any way to call them through Interface definition etc..??

    Regards
    Mayank


    Originally posted in cdnusers.org by mayank
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    archive over 18 years ago

    Mayank,
          To call a task from within a class, one can go via virtual interface:

      interface my_if;
         task my_task;
     //

      class my_c;
        virtual my_if my_if_0;

        task call_task();
           my_if_0.my_task;

    However I've seen tools not fully supporting this yet/premamture support. Till then you are better off with a WA like:

      interface my_if;
         task my_task; endtask


         always @my_trigger begin
             my_task;
         end

    Then trigger this "my_trigger" from within the class.

    This was skeleton code, if you have more problems, show us full code or send it to me via email (ajeetha <> gmail), I will see if I can help.

    HTH
    Ajeetha, CVC
    www.noveldv.com  


    Originally posted in cdnusers.org by ajeetha
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    archive over 18 years ago

    Posted By DM on 3/05/2007 7:12 PM
    Hi, Thanks for the reply. We'll be having a verification environment which includes basic verilog tasks. The upper level sys verilog TB will have to make use of these tasks. So how can I refer to these verilog tasks from sys verilog. Does importing help? or shud we wrap the verilog tasks & use something similar to hdl_task as in Vera??

    DM,
      Depends on how your "upper level SV TB" is modeled, do you use class or module there? One way I showed in reply to Mayank's post.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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