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Calling VHDL procedures in SystemVerilog Testbench.

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Is there a way to call VHDL procedures in a SV TB without translating them into SV tasks.. ?


Originally posted in cdnusers.org by mirzani

  • HI Ajeetha,
      I'll be calling verilog tasks from SV classes. We'll be using VCS for simulations. Do u think this would support what u've suggested in the 1st step (reply to Mayank ).
     or shud i go for the trigger method?
    In the example you have shown, interface & class are SV Files or should the interface be some header/include file. And should the always block be running in the back ground all the time?
    is my_trigger some kind of clock or ??
    Thanks
    Deepa


    Originally posted in cdnusers.org by DM

  • DM,

    I don't knew, whether you have tried this or no, but you can go down to the hierarchy, to the module, from which the task is to be called, and map it at the top.

    Like:

    **************** Code Snippet ***************

    `define DUT top.i_module1

    module top();

    // your TB description

    // To invoke the task in module1

    initial begin
    'DUT.task-name; // "task-name" is the name of the task defined in module-1
    ...
    end

    // module instantiation

    mod-name module1 ( //port mapping );

    ******************************************************************

    This should work.

    - Vivek


    Originally posted in cdnusers.org by prasad_vc

  • Posted By DM on 3/06/2007 5:12 PM
    HI Ajeetha,
      I'll be calling verilog tasks from SV classes. We'll be using VCS for simulations. Do u think this would support what u've suggested in the 1st step (reply to Mayank ).
     or shud i go for the trigger method?
    In the example you have shown, interface & class are SV Files or should the interface be some header/include file. And should the always block be running in the back ground all the time?
    is my_trigger some kind of clock or ??
    Thanks
    Deepa

    Deepa,
          Which VCS version do you use? I'm sure the trigger way would work. Please give it a try yourself or send me an (ajeetha <> gmail) example code, I will fix and send it across.

    BTW, what does VCS have to do with CDNUser forum :-) Your success rate is better if you post in verificationguild.com or www.svug.org


    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha

  • Posted By prasad_vc on 3/06/2007 8:12 PM
    DM,

    I don't knew, whether you have tried this or no, but you can go down to the hierarchy, to the module, from which the task is to be called, and map it at the top.

    Like:

    **************** Code Snippet ***************

    `define DUT top.i_module1

    module top();

    // your TB description

    // To invoke the task in module1

    initial begin
    'DUT.task-name; // "task-name" is the name of the task defined in module-1
    ...
    end

    // module instantiation

    mod-name module1 ( //port mapping );

    ******************************************************************

    This should work.

    - Vivek
    Vivek,
        I would really doubt if it will work in class based environment, AFAIK the class-to-module communication is via virtual interface.

    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha

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