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Calling VHDL procedures in SystemVerilog Testbench.

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Is there a way to call VHDL procedures in a SV TB without translating them into SV tasks.. ?


Originally posted in cdnusers.org by mirzani
Parents

  • DM,

    I don't knew, whether you have tried this or no, but you can go down to the hierarchy, to the module, from which the task is to be called, and map it at the top.

    Like:

    **************** Code Snippet ***************

    `define DUT top.i_module1

    module top();

    // your TB description

    // To invoke the task in module1

    initial begin
    'DUT.task-name; // "task-name" is the name of the task defined in module-1
    ...
    end

    // module instantiation

    mod-name module1 ( //port mapping );

    ******************************************************************

    This should work.

    - Vivek


    Originally posted in cdnusers.org by prasad_vc
Reply

  • DM,

    I don't knew, whether you have tried this or no, but you can go down to the hierarchy, to the module, from which the task is to be called, and map it at the top.

    Like:

    **************** Code Snippet ***************

    `define DUT top.i_module1

    module top();

    // your TB description

    // To invoke the task in module1

    initial begin
    'DUT.task-name; // "task-name" is the name of the task defined in module-1
    ...
    end

    // module instantiation

    mod-name module1 ( //port mapping );

    ******************************************************************

    This should work.

    - Vivek


    Originally posted in cdnusers.org by prasad_vc
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