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SV transaction sequence dependency constraint?

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Hi all, Is there any good methods to write SystemVerilog transaction sequence dependency constraint? For example, in below SV code, I want to always generate IDLE transaction after WRITE (i.e. WRITE after WRITE or READ after WRITE is illegal). //--- SV code start--- //define transactions typedef enum { WRITE=1,READ=2,IDLE=4} cmd_t; class Packet; ... rand cmd_t cmd; ... endclass Packet p; initial repert(20) begin p = new(); p.randomize(); end //--- SV code end--- Best regards, Davy


Originally posted in cdnusers.org by davyzhu
Parents

  • Davy,

    In cases like this, I've been using the "pre_randomize" function as follows...

    //--- SV code start---

    //define transactions
    typedef enum { WRITE=1,READ=2,IDLE=4} cmd_t;
    class Packet;
    ...
    rand cmd_t cmd;
    cmt_t last_cmd = IDLE;
    ...

    constraint c1 {last_cmd == WRITE -> cmd == IDLE;}

    function void pre_randomize();
    last_cmd = cmd;
    endfunction

    endclass

    Packet p;

    initial
    repeat(20) begin
    p = new();
    p.randomize();
    end //--- SV code end

    If someone knows a better way to do this, I'd like to hear about it.

    David Walker


    Originally posted in cdnusers.org by dbwalker0min
Reply

  • Davy,

    In cases like this, I've been using the "pre_randomize" function as follows...

    //--- SV code start---

    //define transactions
    typedef enum { WRITE=1,READ=2,IDLE=4} cmd_t;
    class Packet;
    ...
    rand cmd_t cmd;
    cmt_t last_cmd = IDLE;
    ...

    constraint c1 {last_cmd == WRITE -> cmd == IDLE;}

    function void pre_randomize();
    last_cmd = cmd;
    endfunction

    endclass

    Packet p;

    initial
    repeat(20) begin
    p = new();
    p.randomize();
    end //--- SV code end

    If someone knows a better way to do this, I'd like to hear about it.

    David Walker


    Originally posted in cdnusers.org by dbwalker0min
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