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SV transaction sequence dependency constraint?

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Hi all, Is there any good methods to write SystemVerilog transaction sequence dependency constraint? For example, in below SV code, I want to always generate IDLE transaction after WRITE (i.e. WRITE after WRITE or READ after WRITE is illegal). //--- SV code start--- //define transactions typedef enum { WRITE=1,READ=2,IDLE=4} cmd_t; class Packet; ... rand cmd_t cmd; ... endclass Packet p; initial repert(20) begin p = new(); p.randomize(); end //--- SV code end--- Best regards, Davy


Originally posted in cdnusers.org by davyzhu
Parents

  • Hi Zeev and David,

    Thanks a lot for the good ideas! I have tried David's program and all OK.

    And there is an small errata for above program.
    1. Assume only one instance of the class at one time
    change "cmt_t last_cmd = IDLE;" to "static cmt_t last_cmd = IDLE;"
    2. Change "function void pre_randomize(); " to "function void
    post_randomize(); "

    Best regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
Reply

  • Hi Zeev and David,

    Thanks a lot for the good ideas! I have tried David's program and all OK.

    And there is an small errata for above program.
    1. Assume only one instance of the class at one time
    change "cmt_t last_cmd = IDLE;" to "static cmt_t last_cmd = IDLE;"
    2. Change "function void pre_randomize(); " to "function void
    post_randomize(); "

    Best regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
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