sys. verilog code - need explanation

HI, I am new to s.verilog - any help with the code below will be great!
what does the code below actually mean? anyone explain plz?

why is LOC_IDLE triggered?

LOC :
        begin
          varc_sel[3:0] = { LOC_DRAIN ,
                                  LOC_GETDEL ,
                                  LOC_BUFDEL ,
                                  LOC_IDLE } ;
          case (varc_sel[3:0])
            4'b1000 ,
            4'b0100 ,
            4'b0010 ,
            4'b0001 ,
            4'b0000 :
              begin
               
              end
            default :
              begin
                 $write("ERROR:");
                 $display(" Invalid arc in, fsm:SM, state:LOC") ;
                 $display(" Instance: %m");
                 $display(" Time: %t", $time);