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BFM written in class has to interface with phy signals

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Hi,

I'm new to systemverilog ..and using NCVLOG...and i'm trying interface my BFM modelled using classes with the interface (phy signals)...cadence is not supporting keyword virtual to do this...can anyone help me on how to do this....i want to keep my classes in a separate file...and the top module in a separate file....also have trouble calling the top module from program file....please help ASAP 

Cheers


Originally posted in cdnusers.org by chaitu2k
Parents

  • We won't be supporting globals in the near term. However, you can easily duplicate this behavior using packages, which is a better programming style anyway.

    From IEEE1800 LRM 19.2, "SystemVerilog packages provide an additional mechanism for sharing parameters, data, type, task, function, sequence, and property declarations among multiple SystemVerilog modules, interfaces, and programs. Packages are explicitly named scopes appearing at the outermost level of the source text (at the same level as top-level modules and primitives). Types, variables, tasks, functions, sequences, and properties may be declared within a package. Such declarations may be referenced within modules, macromodules, interfaces, programs, and other packages by either import or fully resolved name. It is also possible to populate packages with parameters, variables, and nets. This may be useful for global items that are not conveniently passed down through the hierarchy."

    package globals;
    class test_c;
    rand bit a;
    endclass
    endpackage

    Then you can import the package wherever you need access to the package contents:

    module test;
    import globals::*;
    test_c item = new;
    endmodule

    Or you can refer to the package items directly:

    module test;
    globals::test_c item = new;
    endmodule

    Tim


    Originally posted in cdnusers.org by tpylant
Reply

  • We won't be supporting globals in the near term. However, you can easily duplicate this behavior using packages, which is a better programming style anyway.

    From IEEE1800 LRM 19.2, "SystemVerilog packages provide an additional mechanism for sharing parameters, data, type, task, function, sequence, and property declarations among multiple SystemVerilog modules, interfaces, and programs. Packages are explicitly named scopes appearing at the outermost level of the source text (at the same level as top-level modules and primitives). Types, variables, tasks, functions, sequences, and properties may be declared within a package. Such declarations may be referenced within modules, macromodules, interfaces, programs, and other packages by either import or fully resolved name. It is also possible to populate packages with parameters, variables, and nets. This may be useful for global items that are not conveniently passed down through the hierarchy."

    package globals;
    class test_c;
    rand bit a;
    endclass
    endpackage

    Then you can import the package wherever you need access to the package contents:

    module test;
    import globals::*;
    test_c item = new;
    endmodule

    Or you can refer to the package items directly:

    module test;
    globals::test_c item = new;
    endmodule

    Tim


    Originally posted in cdnusers.org by tpylant
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