Hi,I'm new to systemverilog ..and using NCVLOG...and i'm trying interface my BFM modelled using classes with the interface (phy signals)...cadence is not supporting keyword virtual to do this...can anyone help me on how to do this....i want to keep my classes in a separate file...and the top module in a separate file....also have trouble calling the top module from program file....please help ASAP Cheers
virtual interfaces will be supported in IUS61, due to be released next month (April).
A workaround is to instantiate your interface and your class at the same level. In the class create a task that can receive a class or struct argument. Then you can collect the signals values from the interface into a class or struct and pass it into the class via the task.
You could also do this via a mailbox. You would pass the mailbox into the class similar to the virtual interface. Although mailboxes aren't natively supported yet (also supported in IUS61), there is a mailbox class that has the same functionality. You can get a copy at http://www.cdnusers.org/Forums/tabid/52/view/topic/forumid/66/postid/2739/Default.aspx.
Hi tpylant,Will the global class be supported in IUS6.1?Best regards,Davy
PHY signals can be declared in interfaces, this interface can be passed as an input to BFM. Declare BFM as a module. Instead of declaring classes alone in a file, declare them in a package and then import this package whereever required.Also, in the top module, use full hierarichal path to call a particular module.Cheers
We won't be supporting globals in the near term. However, you can easily duplicate this behavior using packages, which is a better programming style anyway. From IEEE1800 LRM 19.2, "SystemVerilog packages provide an additional mechanism for sharing parameters, data, type, task, function, sequence, and property declarations among multiple SystemVerilog modules, interfaces, and programs. Packages are explicitly named scopes appearing at the outermost level of the source text (at the same level as top-level modules and primitives). Types, variables, tasks, functions, sequences, and properties may be declared within a package. Such declarations may be referenced within modules, macromodules, interfaces, programs, and other packages by either import or fully resolved name. It is also possible to populate packages with parameters, variables, and nets. This may be useful for global items that are not conveniently passed down through the hierarchy."package globals; class test_c; rand bit a; endclassendpackageThen you can import the package wherever you need access to the package contents:module test; import globals::*; test_c item = new;endmoduleOr you can refer to the package items directly:module test; globals::test_c item = new;endmoduleTim
Hi tpylant,Thanks so much for the instant help!I understand. I used to encapsulate class in module(cannot re-use outside), and I will encapsulate class in package from now on.There are two questions: For I used to force (through Tcl) signals in Verilog, can I force variable in class instance in IUS? I am reading the uRM, but I'd like to wait for the Class-based version available. I notice the transaction layer is implemented by interface (maybe more intuitive for design engineer, but is not very good for verification engineer). Is there any article by Cadence tell us how to implement simple transaction layer by class in IUS(for example, how to pass transaction here and there by class), any recommendation methodology is welcome!Best regards,Davy