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  3. BFM written in class has to interface with phy signals

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BFM written in class has to interface with phy signals

archive
archive over 18 years ago

Hi,

I'm new to systemverilog ..and using NCVLOG...and i'm trying interface my BFM modelled using classes with the interface (phy signals)...cadence is not supporting keyword virtual to do this...can anyone help me on how to do this....i want to keep my classes in a separate file...and the top module in a separate file....also have trouble calling the top module from program file....please help ASAP 

Cheers


Originally posted in cdnusers.org by chaitu2k
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  • archive
    archive over 18 years ago

    Hi tpylant,

    Thanks so much for the instant help!

    I understand. I used to encapsulate class in module(cannot re-use outside), and I will encapsulate class in package from now on.

    There are two questions:
    [1] For I used to force (through Tcl) signals in Verilog, can I force variable in class instance in IUS?
    [2] I am reading the uRM, but I'd like to wait for the Class-based version available.
    I notice the transaction layer is implemented by interface (maybe more intuitive for design engineer, but is not very good for verification engineer).
    Is there any article by Cadence tell us how to implement simple transaction layer by class in IUS(for example, how to pass transaction here and there by class), any recommendation methodology is welcome!

    Best regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
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  • archive
    archive over 18 years ago

    Hi tpylant,

    Thanks so much for the instant help!

    I understand. I used to encapsulate class in module(cannot re-use outside), and I will encapsulate class in package from now on.

    There are two questions:
    [1] For I used to force (through Tcl) signals in Verilog, can I force variable in class instance in IUS?
    [2] I am reading the uRM, but I'd like to wait for the Class-based version available.
    I notice the transaction layer is implemented by interface (maybe more intuitive for design engineer, but is not very good for verification engineer).
    Is there any article by Cadence tell us how to implement simple transaction layer by class in IUS(for example, how to pass transaction here and there by class), any recommendation methodology is welcome!

    Best regards,
    Davy


    Originally posted in cdnusers.org by davyzhu
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