BFM written in class has to interface with phy signals

1) I cannot see the class hierarchy from TCL. Therefore, you can't deposit onto a class property. The only thing I can think of off the top of my head is to create local variables that you can deposit onto and then connect those variable to the corresponding class properties. Or if you're able, you can make the class properties static which would make them available to TCL (deposit class_name::prop = 0).

2) Our class-based implementation of URM is just going into limited production. If you want to learn more about it, you will need to contact your local sales or AE. However, we have had a number of successes with our module-based implementation. As you noticed, it uses module and interfaces to construct the environment but takes advantage of classes for generating the data. This has proved successful because it is very quick to implement a solution (can put together an env for a block in 1-2 days) and easy for users comfortable with Verilog to understand and debug.

Since you are already reading URM, I would suggest implementing the same methodology but using classes in place of modules, mailboxes instead of the BFM interface and a virtual interface for the DUT interface. That will give you a very simplistic example of how our URM class-based implementation will work. However, the base class libraries that come with URM will give you much more automation and power than that simple example.

Tim

1) I cannot see the class hierarchy from TCL. Therefore, you can't deposit onto a class property. The only thing I can think of off the top of my head is to create local variables that you can deposit onto and then connect those variable to the corresponding class properties. Or if you're able, you can make the class properties static which would make them available to TCL (deposit class_name::prop = 0).

2) Our class-based implementation of URM is just going into limited production. If you want to learn more about it, you will need to contact your local sales or AE. However, we have had a number of successes with our module-based implementation. As you noticed, it uses module and interfaces to construct the environment but takes advantage of classes for generating the data. This has proved successful because it is very quick to implement a solution (can put together an env for a block in 1-2 days) and easy for users comfortable with Verilog to understand and debug.

Since you are already reading URM, I would suggest implementing the same methodology but using classes in place of modules, mailboxes instead of the BFM interface and a virtual interface for the DUT interface. That will give you a very simplistic example of how our URM class-based implementation will work. However, the base class libraries that come with URM will give you much more automation and power than that simple example.

Tim