BFM written in class has to interface with phy signals

>> what's "I cannot see the class hierarchy from TCL" mean? Will the future IUS Tcl supports
>> force signals in class instance directly? (You see, a lot of old verification methodology
>> change the scenario through Tcl force)

IMHO you better change that mindset and methodology - enabling TCL inherently means compromise on performance. With SV providing you enough constrained based generation, rely on it and wrap it using a good methodology say uRM (or VMM or anything - under the hood lot of things are common indeed). So why "force" class members to have a specifc value? In a VMM style thing I can do this easily in a test case as:

program my_test_pgm;
  my_env env_0;

  initial begin : test
    env_0 = new();
    env_0.build();
    env_0.generator_0.class_to_be_changed = ;
    env_0.run();
  end : test
endprogram : my_test_pgm

Point is - you can achieve the same that you would get via force in a much more "standard" way than force. Another important thing - by relyhing on force you are having your TB tool specific - why do you want to do that?

If your argument is "TCL" is run time - there are several WA for that, tools may give you better ways, for instance Specman has an excellent way of handling it and am sure NCSIM can extend that for SV in future.

Finally - it is methodology than "can I do it", so adopt a good methodology with SV.

My 2 cents!
Ajeetha, CVC
www.noveldv.com

>> what's "I cannot see the class hierarchy from TCL" mean? Will the future IUS Tcl supports
>> force signals in class instance directly? (You see, a lot of old verification methodology
>> change the scenario through Tcl force)

IMHO you better change that mindset and methodology - enabling TCL inherently means compromise on performance. With SV providing you enough constrained based generation, rely on it and wrap it using a good methodology say uRM (or VMM or anything - under the hood lot of things are common indeed). So why "force" class members to have a specifc value? In a VMM style thing I can do this easily in a test case as:

program my_test_pgm;
  my_env env_0;

  initial begin : test
    env_0 = new();
    env_0.build();
    env_0.generator_0.class_to_be_changed = ;
    env_0.run();
  end : test
endprogram : my_test_pgm

Point is - you can achieve the same that you would get via force in a much more "standard" way than force. Another important thing - by relyhing on force you are having your TB tool specific - why do you want to do that?

If your argument is "TCL" is run time - there are several WA for that, tools may give you better ways, for instance Specman has an excellent way of handling it and am sure NCSIM can extend that for SV in future.

Finally - it is methodology than "can I do it", so adopt a good methodology with SV.

My 2 cents!
Ajeetha, CVC
www.noveldv.com