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  3. ncelab: *F,INTERR: INTERNAL ERROR , debug

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ncelab: *F,INTERR: INTERNAL ERROR , debug

archive
archive over 18 years ago

Hi,

Could anyone help to debug this issue is it a tool issue or code issue.....

I'm getting the following error for simulation....the code compiles fine..i have written a separate interface file along with clocking block in it....code for interface file is not shown here.....

ncelab: *F,INTERR: INTERNAL ERROR
TOOL: ncelab 05.82-p002



`timescale 1ns/1ns
module top;
bit Clk24 = 0;
bit ResetN = 0;

always #12 Clk24 = ~Clk24;

gfsktx_top_if tx_gfsk_if(Clk24);


GfskTxTop dut ( .Clk(Clk24),
                .ResetN(tx_gfsk_if.ResetN),
                .S2PIn(tx_gfsk_if.S2PIn),
                .ValidIn(tx_gfsk_if.ValidIn),
  .TxEnable(tx_gfsk_if.TxEnable),
                .Gfsk2DacI(tx_gfsk_if.Gfsk2DacI),
  .Gfsk2DacQ(tx_gfsk_if.Gfsk2DacQ),
                .ValidOut(tx_gfsk_if.ValidOut)
                  );

//classes
class gfsktx_bfm;

 //virtual gfsktx_top_if sigs;
       
 //function new
 //function new(virtual gfsktx_top_if sigs);
 // tx_gfsk_if = sigs;
 //endfunction: new

 //task reset sequence
 task resetsequence();
 
  //semaphore sem = new(1);
  //if(!sem.try_get(1)) $stop;

  $write("task reset sequence entered\n");
  tx_gfsk_if.ResetN  
  tx_gfsk_if.S2PIn  
  tx_gfsk_if.TxEnable 
  tx_gfsk_if.ValidIn 
  repeat (2) @top.Clk24;
  
 
  //sem.put(1);

 endtask: resetsequence
 
 //checking reset
 task resetcheck();

  //semaphore sem_1 = new(1);
  //if(!sem_1.try_get(1)) $stop;
 
  @Clk24;
  assert(tx_gfsk_if.Gfsk2DacQ == 'b0);
  assert(tx_gfsk_if.Gfsk2DacI == 'b0);
  assert(tx_gfsk_if.ValidOut == 1'b0);
  @Clk24;

  //sem_1.put(1);

 endtask: resetcheck

 task load_data(integer count);
  int cnt;

  cnt = count;
 
  //semaphore sem_2 = new(1);
  //if(!sem_2.try_get(1)) $stop;

  tx_gfsk_if.ResetN  
  tx_gfsk_if.S2PIn 
  tx_gfsk_if.TxEnable 

  while(cnt != 0)
  begin
   tx_gfsk_if.ValidIn 
   @Clk24;
   tx_gfsk_if.ValidIn 
   repeat(23)@Clk24;
   cnt--;
  end

 endtask: load_data


endclass: gfsktx_bfm

gfsktx_bfm gfsktx;
//gfsktx_test gfsktx_test();
initial
 begin
  gfsktx.resetsequence();
  repeat(20) @Clk24;
  gfsktx.resetcheck();
  repeat(20) @Clk24;
  gfsktx.load_data(20);
  repeat(300) @Clk24;
  $finish;
 end  
endmodule: top


Originally posted in cdnusers.org by chaitu2k
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  • archive
    archive over 18 years ago

    Hello,

    I noticed that you are running with the IUS5.82-p002 release so first I suggest you try to get the latest release.

    I added an empty DUT and a simple interface definition to you test and it ran without an internal error.. Just two assertion errors.

    So... the problem could be in the interface definition or the DUT. I've attached my simple files. Try running with this on your testcase so we can determine if the problem is with the IUS5.82 release or the other code.

    interface gfsktx_top_if(input bit clk);
    logic ResetN, S2PIn, ValidIn, TxEnable, Gfsk2DacI, Gfsk2DacQ, ValidOut;
    endinterface : gfsktx_top_if

    module GfskTxTop (input bit Clk, ResetN, S2PIn, ValidIn, TxEnable, Gfsk2DacI, Gfsk2DacQ, output bit ValidOut);
    endmodule


    Originally posted in cdnusers.org by kameade
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  • archive
    archive over 18 years ago

    Hello,

    I noticed that you are running with the IUS5.82-p002 release so first I suggest you try to get the latest release.

    I added an empty DUT and a simple interface definition to you test and it ran without an internal error.. Just two assertion errors.

    So... the problem could be in the interface definition or the DUT. I've attached my simple files. Try running with this on your testcase so we can determine if the problem is with the IUS5.82 release or the other code.

    interface gfsktx_top_if(input bit clk);
    logic ResetN, S2PIn, ValidIn, TxEnable, Gfsk2DacI, Gfsk2DacQ, ValidOut;
    endinterface : gfsktx_top_if

    module GfskTxTop (input bit Clk, ResetN, S2PIn, ValidIn, TxEnable, Gfsk2DacI, Gfsk2DacQ, output bit ValidOut);
    endmodule


    Originally posted in cdnusers.org by kameade
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