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vhdl & system verilog

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   Hi All,

I have a very basic qn - jus picking up system. verilog -> if the testbench is in system verilog
and the top level is in vhdl - will both the modules be able to talk to each other?

Many Thanks in advance,
indeb


Originally posted in cdnusers.org by indeb
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  • Hi Indeb,
    Yes, this should work - though not defined by LRM per-se, many tools support this Mixed mode sim nicely. My experience with NC is few years old, even then it supported VHDL-Verilog cosim nicely. So at the worst case the following should work for you:

    SV_Testbench --> Verilog Top --> VHDL DUT


    Top Level in VHDL with say a SV Program instantiated also works in other simulators BTW.

    HTH
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
Reply

  • Hi Indeb,
    Yes, this should work - though not defined by LRM per-se, many tools support this Mixed mode sim nicely. My experience with NC is few years old, even then it supported VHDL-Verilog cosim nicely. So at the worst case the following should work for you:

    SV_Testbench --> Verilog Top --> VHDL DUT


    Top Level in VHDL with say a SV Program instantiated also works in other simulators BTW.

    HTH
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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